PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889874
1:2
D
IFFERENTIAL
-
TO
-LVPECL B
UFFER
/D
IVIDER
F
EATURES
•
Two LVPECL outputs
•
Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16
•
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
•
Output frequency: > 2.5GHz
•
Output skew: 5ps (typical)
•
Part-to-part skew: TBD
•
Additive jitter, RMS: <0.03ps (design target)
•
Supply voltage range: (LVPECL), 2.375V to 3.465V
Supply voltage range: (ECL), -3.465V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS889874 is a high speed 1:2 Differential-
to-LVPECL Buffer/Divider and is a member of
HiPerClockS™
the HiPerClockS
™
family of high performance
clock solutions from ICS. The ICS889874 has
a selectable
÷1, ÷2, ÷4, ÷8, ÷16
output divider,
which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several
differential signal types while minimizing the number of
required external components. The device is packaged in
a small, 3mm x 3mm VFQFN package, making it ideal for
use on space-constrained boards.
IC
S
B
LOCK
D
IAGRAM
S2
P
IN
A
SSIGNMENT
V
CC
S0
Q0
nRESET
Enable
FF
Enable
MUX
1
2
3
4
16 15 14 13
12
11
10
9
5
S2
S1
V
EE
IN
V
T
V
REF
_
AC
nIN
nQ0
Q1
Q0
0
nQ1
6
nc
7
V
CC
8
nRESET
REV. A MARCH 20, 2006
nQ0
1
IN
V
T
nIN
S0
Decoder
Q1
nQ1
00
01
10
11
÷2
÷4
÷8
÷16
ICS889874
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
S1
V
REF_AC
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889874AK
www.icst.com/products/hiperclocks.html
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889874
1:2
D
IFFERENTIAL
-
TO
-LVPECL B
UFFER
/D
IVIDER
Type
Description
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Pullup
Select pins. LVCMOS/LVTTL interface levels.
No connect.
Positive supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider. When
HIGH, unconnected. Input threshold is V
CC
/2V. Includes a 37k
Ω
pull-up
resistor. LVTTL / LVCMOS interface levels.
Inver ting differential LVPECL clock input.
Reference voltage for AC-coupled applications.
Termination input.
Non-inver ting LVPECL differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 15, 16
6
7, 14
8
9
10
11
12
Name
Q0, nQ0
Q1, nQ1
S2, S1, S0
nc
V
CC
nRESET
nIN
V
REF_AC
V
T
IN
Output
Output
Input
Unused
Power
Input
Input
Output
Input
Input
Pullup
13
V
EE
Power
Negative supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
889874AK
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889874
1:2
D
IFFERENTIAL
-
TO
-LVPECL B
UFFER
/D
IVIDER
Outputs
Q0, Q1
Disabled; LOW
nQ0, nQ1
Disabled; HIGH
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
nRESET
0
Selected Source
IN, nIN
1
IN, nIN
Enabled
Enabled
NOTE: After nRESET switches, the clock outputs are disabled or enabled following a
falling input clock edge as shown in
Figur
e
1.
V
CC
/2
nRESET
IN
nIN
t
RR
V
IN
t
PD
nQ
Q
V
OUT
Swing
F
IGURE
1. nRESET T
IMING
D
IAGRAM
(
WHEN
S2 = 1)
T
ABLE
3B. T
RUTH
T
ABLE
Inputs
nRESET
1
1
1
1
1
S2
0
1
1
1
1
S1
X
0
0
1
1
S0
X
0
1
0
1
Outputs
Reference Clock (pass through)
Reference Clock ÷2
Reference Clock ÷4
Reference Clock ÷8
Reference Clock ÷16
Q = LOW, nQ = HIGH
0
1
X
X
Clock Disable; (NOTE 1)
Q = LOW, nQ = HIGH
0
0
X
X
Clock Disable; (NOTE 1)
NOTE 1: Reset/Disable function is asser ted on the next clock input
(IN/nIN) high-to-low transition.
889874AK
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889874
1:2
D
IFFERENTIAL
-
TO
-LVPECL B
UFFER
/D
IVIDER
-0.5V to +4.0V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
±50mA
±100mA
± 0.5mA
-65°C to 150°C
51.5°C/W (0 lfpm)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current IN, nIN
V
T
Current, I
VT
V
REF_AC
Sink/Source, I
VREF_AC
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±10%
OR
2.5V±5%; T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
50
Maximum
3.63
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±10%
OR
2.5V±5%; T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
CC
= V
IN
= 3.63V
V
CC
= 3.63V, V
IN
= 0V
Test Conditions
Minimum
2
0
-125
Typical
Maximum
V
CC
+ 0.3
0.8
20
-300
Units
V
V
µA
µA
T
ABLE
4C. DC C
HARACTERISTICS
,
V
CC
= 3.3V±10%
OR
2.5V±5%; T
A
= -40°C
TO
85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current
Bias Voltage
(IN, nIN)
V
CC
- 1.35
(IN, nIN)
(IN, nIN)
(IN, nIN)
1.2
0
0.15
0.3
45
Test Conditions
Minimum
Typical
100
V
CC
V
CC
- 0.15
2.8
Maximum
Units
Ω
V
V
V
V
mA
V
889874AK
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889874
1:2
D
IFFERENTIAL
-
TO
-LVPECL B
UFFER
/D
IVIDER
Conditions
Minimum
Typical
V
CC
- 1.005
V
CC
- 1.78
800
1.60
Maximum
Units
mV
mV
mV
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±10%
OR
2.5V±5%; T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage Swing
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±10%
OR
2.5V±5%; T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
RR
t
R
/t
F
t
S
t
H
Parameter
Maximum Output Frequency
Maximum Input Frequency
Propagation Delay, (Differential);
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Reset Recover y Time
Output Rise/Fall Time
Clock Enable Setup Time
Clock Enable Hold Time
EN to IN, nIN
EN to IN, nIN
20% to 80%
Condition
Output Swing
≥
450mV
÷ 2, ÷4, ÷8, ÷16
Input Swing: < 400mV
Input Swing:
≥
400mV
Minimum
2
2
72 5
725
5
TBD
<0.03
TBD
180
TBD
TBD
Typical
Maximum
Units
GHz
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
All parameters characterized at
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
889874AK
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 20, 2006
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
