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Virtex-4 Family Overview
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DS112 (v3.1) August 30, 2010
Product Specification
General Description
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4
family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC
technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and
combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the
PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a
state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.
Summary of Virtex-4 Family Features
•
Three Families — LX/SX/FX
-
-
-
Virtex-4 LX: High-performance logic applications solution
Virtex-4 SX: High-performance solution for digital signal
processing (DSP) applications
Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
Digital clock manager (DCM) blocks
Additional phase-matched clock dividers (PMCD)
Differential global clocks
18 x 18, two’s complement, signed Multiplier
Optional pipeline stages
Built-in Accumulator (48-bit) and Adder/Subtracter
Distributed RAM
Dual-port 18-Kbit RAM blocks
·
Optional pipeline stages
·
Optional programmable FIFO logic automatically
remaps RAM signals as FIFO signals
High-speed memory interface supports DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
•
SelectIO™ Technology
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-
-
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1.5V to 3.3V I/O operation
Built-in ChipSync™ source-synchronous technology
Digitally controlled impedance (DCI) active termination
Fine grained I/O banking (configuration in one bank)
•
Xesium™ Clock Technology
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•
XtremeDSP™ Slice
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•
•
•
•
•
•
•
•
•
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Smart RAM Memory Hierarchy
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Flexible Logic Resources
Secure Chip AES Bitstream Encryption
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging including Pb-Free Package
Choices
RocketIO™ 622 Mb/s to 6.5 Gb/s Multi-Gigabit
Transceiver (MGT) [FX
only]
IBM PowerPC RISC Processor Core [FX
only]
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PowerPC 405 (PPC405) Core
Auxiliary Processor Unit Interface (User Coprocessor)
Multiple Tri-Mode Ethernet MACs [FX
only]
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Table 1:
Virtex-4 FPGA Family Members
Configurable Logic Blocks (CLBs)
(1)
Array
(3)
Row x Col
Logic
Cells
Block RAM
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total Max
I/O
User
Banks I/O
Device
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VLX100
XC4VLX160
Slices
PowerPC
Max
Max
Processor
Distributed
XtremeDSP
18 Kb
Block
Slices
(2)
Blocks RAM (Kb)
DCMs PMCDs
Blocks
RAM (Kb)
64 x 24
96 x 28
128 x 36
128 x 52
160 x 56
192 x 64
192 x 88
13,824
24,192
41,472
59,904
80,640
6,144
10,752
18,432
26,624
35,840
96
168
288
416
560
768
1056
1392
32
48
64
64
80
96
96
96
48
72
96
160
200
240
288
336
864
1,296
1,728
2,880
3,600
4,320
5,184
6,048
4
8
8
8
12
12
12
12
0
4
4
4
8
8
8
8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
9
11
13
13
15
17
17
17
320
448
640
640
768
960
960
960
110,592 49,152
152,064 67,584
XC4VLX200 192 x 116 200,448 89,088
© Copyright 2004–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
DS112 (v3.1) August 30, 2010
Product Specification
www.xilinx.com
1
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Virtex-4 Family Overview
Table 1:
Virtex-4 FPGA Family Members
(Continued)
Configurable Logic Blocks (CLBs)
(1)
Array
(3)
Row x Col
Logic
Cells
Block RAM
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total Max
I/O
User
Banks I/O
Device
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
Slices
PowerPC
Max
Max
Processor
Distributed
XtremeDSP
18 Kb
Block
Slices
(2)
Blocks RAM (Kb)
DCMs PMCDs
Blocks
RAM (Kb)
64 x 40
96 x 40
128 x 48
64 x 24
64 x 36
96 x 52
128 x 52
160 x 68
192 x 84
23,040
34,560
55,296
12,312
19,224
41,904
56,880
94,896
10,240
15,360
24,576
5,472
8,544
18,624
25,280
42,176
160
240
384
86
134
291
395
659
987
128
192
512
32
32
48
128
160
192
128
192
320
36
68
144
232
376
552
2,304
3,456
5,760
648
1,224
2,592
4,176
6,768
9,936
4
8
8
4
4
8
12
12
20
0
4
4
0
0
4
8
8
8
N/A
N/A
N/A
1
1
2
2
2
2
N/A
N/A
N/A
2
2
4
4
4
4
N/A
N/A
N/A
N/A
8
12
16
20
24
9
11
13
9
9
11
13
15
17
320
448
640
320
320
448
576
768
896
142,128 63,168
Notes:
1.
One CLB = Four Slices = Maximum of 64 bits.
2.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
3.
Some of the row/column array is used by the processors in the FX devices.
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
•
Up to twenty Digital Clock Manager (DCM) modules
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-
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Precision clock deskew and phase shift
Flexible frequency synthesis
Dual operating modes to ease performance trade-off
decisions
Improved maximum input/output frequency
Improved phase shifting resolution
Reduced output jitter
Low-power operation
Enhanced phase detectors
Wide phase shift range
500 MHz XtremeDSP Slices
•
•
•
•
•
•
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
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Full and Empty Flag support
Fully programmable AF and AE Flags
Synchronous/ Asynchronous Operation
•
•
•
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Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
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Up to 178,176 internal registers with clock enable
(XC4VLX200)
Up to 178,176 look-up tables (LUTs)
Logic expanding multiplexers and I/O registers
500 MHz Integrated Block Memory
•
•
•
Flexible Logic Resources
•
•
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•
•
•
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Cascadable variable shift registers or distributed
memory capability
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
DS112 (v3.1) August 30, 2010
Product Specification
www.xilinx.com
2
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Virtex-4 Family Overview
SelectIO Technology
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Up to 960 user I/Os
Wide selections of I/O standards from 1.5V to 3.3V
Extremely high-performance
-
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600 Mb/s HSTL & SSTL (on all single-ended I/O)
1 Gb/s LVDS (on all differential I/O pairs)
Digitally Controlled Impedance (DCI)
Active I/O Termination
•
•
•
•
•
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Optional series or parallel termination
Temperature compensation
256-bit AES bitstream decryption provides intellectual
property (IP) security
Improved bitstream error detection/correction capability
Fast SelectMAP configuration
JTAG support
Readback capability
Configuration
True differential termination
Selected low-capacitance I/Os for improved signal
integrity
Same edge capture at input and output I/Os
Memory interface support for DDR and DDR-2
SDRAM, QDR-II, and RLDRAM-II.
Integrated with SelectIO technology to simplify
source-synchronous interfaces
Per-bit deskew capability built in all I/O blocks (variable
input delay line)
Dedicated I/O and regional clocking resources (pin and
trees)
Built in data serializer/deserializer logic in all I/O and
clock dividers
Memory/Networking/Telecommunication interfaces up
to 1 Gb/s+ DDR
ChipSync Technology
•
•
•
•
•
90 nm Copper CMOS Process
1.2V Core Voltage
Flip-Chip Packaging
•
Pb-Free packages available with production devices.
System Blocks Specific to the Virtex-4 FX Family
RocketIO Multi-Gigabit Transceiver (MGT)
•
•
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•
•
Full-duplex serial transceiver (MGT) capable of
622 Mb/s to 6.5 Gb/s baud rates
8B/10B, 64B/66B, user-defined FPGA logic, or no data
encoding/decoding
Channel bonding support
CRC generation and checking
Programmable TX pre-emphasis or pre-equalization
Programmable RX continuous time equalization
Programmable RX decision feedback equalization
On-chip RX AC coupling
RX signal detect and loss of signal indicator
TX driver electrical idle mode
User dynamic reconfiguration using secondary
configuration bus
Embedded PowerPC 405 processor (PPC405) core
-
-
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Up to 450 MHz operation
Five-stage data path pipeline
16 KB instruction cache
16 KB data cache
•
Auxiliary Processor Unit (APU) Interface for direct
connection from PPC405 to coprocessors in fabric
-
-
-
-
APU can run at different clock rates
Supports autonomous instructions: no pipeline stalls
32-bit instruction and 64-bit data
4-cycle cache line transfer
Tri-Mode Ethernet Media Access Controller
•
•
•
•
•
•
•
•
•
•
•
IEEE 802.3 compliant
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-detect
Receive address filter
Fully monolithic 1000Base-X solution with RocketIO
MGT
Implements SGMII through RocketIO MGT to external
PHY device
Supports multiple PHY (MII, GMII, etc.) interfaces
through an I/O resource
Receive and transmit statistics available through
separate interfaces
Separate host and client interfaces
Support for jumbo frames
Flexible, user-configurable host interface
PowerPC 405 Processor RISC Core
•
-
-
Enhanced instruction and data on-chip memory
(OCM) controllers
Additional frequency ratio options between
PPC405 and Processor Local Bus
DS112 (v3.1) August 30, 2010
Product Specification
www.xilinx.com
3
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Virtex-4 Family Overview
Architectural Description: Virtex-4 FPGA Array Overview
Virtex-4 devices are user-programmable gate arrays with
various configurable elements and embedded cores opti-
mized for high-density and high-performance system
designs. Virtex-4 devices implement the following function-
ality:
•
I/O blocks provide the interface between package pins
and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by
programmable I/O blocks (IOBs). The IOBs are
enhanced for source-synchronous applications.
Source-synchronous optimizations include per-bit
deskew, data serializer/deserializer, clock dividers, and
dedicated local clocking resources.
Configurable Logic Blocks (CLBs), the basic logic
elements for Xilinx FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and
SRL16 shift register capability.
Block RAM modules provide flexible 18Kbit true
dual-port RAM, that are cascadable to form larger
memory blocks. In addition, Virtex-4 FPGA block RAMs
contain optional programmable FIFO logic for
increased device utilization.
Cascadable embedded XtremeDSP slices with 18-bit x
18-bit dedicated multipliers, integrated Adder, and
48-bit accumulator.
•
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock
multiplication/division, and coarse-/fine-grained clock
phase shifting.
Additionally, FX devices support the following embedded
system functionality:
•
•
Integrated high-speed serial transceivers enable data
rates up to 6.5 Gb/s per channel.
Embedded IBM PowerPC 405 Processor RISC CPU
(up to 450 MHz) with the auxiliary processor unit
interface
10/100/1000 Ethernet media-access control (EMAC)
cores.
•
•
•
The general routing matrix (GRM) provides an array of rout-
ing switches between each component. Each programma-
ble element is tied to a switch matrix, allowing multiple
connections to the general routing matrix. The overall pro-
grammable interconnection is hierarchical and designed to
support high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
•
Virtex-4 FPGA Features
This section briefly describes the features of the Virtex-4 family of FPGAs.
Input/Output (SelectIO) Blocks
IOBs are programmable and can be categorized as follows:
•
•
•
•
•
•
•
Programmable single-ended or differential (LVDS)
operation
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register
Bidirectional block
Per-bit deskew circuitry
Dedicated I/O and regional clocking resources
Built in data serializer/deserializer
•
•
HSTL 1.5V and 1.8V (Class I, II, III, and IV)
SSTL 1.8V and 2.5V (Class I and II)
The DCI I/O feature can be configured to provide on-chip
termination for each single-ended I/O standard and some
differential I/O standards.
The IOB elements also support the following differential sig-
naling I/O standards:
•
•
•
•
•
•
LVDS and Extended LVDS (2.5V only)
BLVDS (Bus LVDS)
ULVDS
Hypertransport™
Differential HSTL 1.5V and 1.8V (Class II)
Differential SSTL 1.8V and 2.5V (Class II)
The IOB registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended standards:
•
•
•
•
•
LVTTL
LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI (33 and 66 MHz)
PCI-X
GTL and GTLP
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Per-bit deskew circuitry allows for programmable signal
delay internal to the FPGA. Per-bit deskew flexibly provides
fine-grained increments of delay to carefully produce a
DS112 (v3.1) August 30, 2010
Product Specification
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4
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Virtex-4 Family Overview
range of signal delays. This is especially useful for synchro-
nizing signal edges in source synchronous interfaces.
General purpose I/O in select locations (four per bank) are
designed to be “regional clock capable” I/O by adding spe-
cial hardware connections for I/O in the same locality. These
regional clock inputs are distributed within a limited region
to minimize clock skew between IOBs. Regional I/O clock-
ing supplements the global clocking resources.
Data serializer/deserializer capability is added to every I/O
to support source synchronous interfaces. A serial-to-paral-
lel converter with associated clock divider is included in the
input path, and a parallel-to-serial converter in the output
path.
An in-depth guide to the Virtex-4 FPGA IOB is discussed in
the
Virtex-4 FPGA User Guide.
XtremeDSP Slices
The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s
complement signed multiplier, adder logic, and a 48-bit
accumulator. Each multiplier or accumulator can be used
independently. These blocks are designed to implement
extremely efficient and high-speed DSP applications.
The block DSP feature in Virtex-4 devices are further dis-
cussed in
XtremeDSP Design Considerations.
Global Clocking
The DCM and global-clock multiplexer buffers provide a
complete solution for designing high-speed clock networks.
Up to twenty DCM blocks are available. To generate
deskewed internal or external clocks, each DCM can be
used to eliminate clock distribution delay. The DCM also
provides 90°, 180°, and 270° phase-shifted versions of the
output clocks. Fine-grained phase shifting offers higher res-
olution phase adjustment with fraction of the clock period
increments. Flexible frequency synthesis provides a clock
output frequency equal to a fractional or integer multiple of
the input clock frequency.
Virtex-4 devices have 32 global-clock MUX buffers. The
clock tree is designed to be differential. Differential clocking
helps reduce jitter and duty cycle distortion.
Configurable Logic Blocks (CLBs)
A CLB resource is made up of four slices. Each slice is
equivalent and contains:
•
•
•
•
•
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Fast carry look-ahead chain
The function generators F & G are configurable as 4-input
look-up tables (LUTs). Two slices in a CLB can have their
LUTs configured as 16-bit shift registers, or as 16-bit distrib-
uted RAM. In addition, the two storage elements are either
edge-triggered D-type flip-flops or level sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
The Virtex-4 FPGA CLBs are further discussed in the
Virtex-4 FPGA User Guide.
Routing Resources
All components in Virtex-4 devices use the same intercon-
nect scheme and the same access to the global routing
matrix. Timing models are shared, greatly improving the
predictability of the performance for high-speed designs.
Boundary-Scan
Boundary-Scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-4 devices, complying with IEEE standards
1149.1 and 1532.
Block RAM
The block RAM resources are 18 Kb true dual-port RAM
blocks, programmable from 16K x 1 to 512 x 36, in various
depth and width configurations. Each port is totally synchro-
nous and independent, offering three “read-during-write”
modes. Block RAM is cascadable to implement large
embedded storage blocks. Additionally, back-end pipeline
registers, clock control circuitry, built-in FIFO support, and
byte write enable are new features supported in the Virtex-4
FPGA.
The block RAM feature in Virtex-4 devices is further dis-
cussed in the
Virtex-4 FPGA User Guide.
Configuration
Virtex-4 devices are configured by loading the bitstream into
internal configuration memory using one of the following
modes:
•
•
•
•
•
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE-1532)
Optional 256-bit AES decryption is supported on-chip (with
software bitstream encryption) providing Intellectual Prop-
erty security.
DS112 (v3.1) August 30, 2010
Product Specification
www.xilinx.com
5
FPGA/CPLD
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