PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843206I
G
ENERAL
D
ESCRIPTION
The ICS843206I is a 6 output LVPECL Synthesizer
optimized to generate Gigabit Ethernet and SONET
HiPerClockS™
reference clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from IDT. Using a 19.44MHz and 25MHz,
18pF parallel resonant crystal, 155.52MHz and 156.25MHz
frequencies can be generated. The ICS843206I uses IDT’s
FemtoClock
TM
low phase noise VCO technology and can achieve
1ps or lower typical RMS phase jitter. The ICS843206I is pack-
aged in a 48-pin TSSOP package.
F
EATURES
• Six 3.3V differential LVPECL output pairs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 155.52MHz
and 156.25MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz – 1.3MHz): 1.08ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.5ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
OEA
Pullup
QA0
nQA0
P
IN
A
SSIGNMENT
nPLL_BYPASS_AB
Pullup
QA1
OEB
Pullup
REF_CLKAB
XTAL_IN0
XTAL_OUT0
REF_SELAB
Pullup
Pulldown
25MHz
0
PLL
625MHz
÷4
156.25MHz
OSC
1
SELC0
Pullup
OEC0
Pullup
REF_CLKC
XTAL_IN1
XTAL_OUT1
Pulldown
0
0
19.44MHz
PLL
OSC
622.08MHz
÷4
155.52MHz
1
OEC1
nQA1
QA1
nQA0
QA0
nc
QB0
V
CCO
_
AB
QB0
nQB0
nQB0
nPLL_BYPASS_AB
QB1
QB1
nQB1
nQB1
nc
nc
XTAL_IN1
XTAL_OUT1
REF_CLKC
REF_SELC
nPLL_BYPASS_C
V
CCO
_
C
nc
QC0
QC0
nQC0
QC1
nQC0
nQC1
nQA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF_SELAB
REF_CLKAB
XTAL_IN0
XTAL_OUT0
nc
V
EE
OEA
OEB
V
CC
V
CCA
nc
nc
SELC0
V
EE
OEC0
OEC1
V
CC
SELC1
V
CCA
nc
nc
nc
nc
nc
1
0
ICS843206I
QC1
nQC1
Pullup
REF_SELC
Pullup
nPLL_BYPASS_C
Pullup
1
Pullup
48 Lead TSSOP
6.1mm x 12.5mm x 0.93mm
package body
G Package
Top View
SELC1
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843206AGI REV. A MAY 6, 2008
ICS843206I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 12, 13, 20,
25, 26, 27, 28,
29, 37, 38, 44
6
7, 8
9
10, 11
14,
15
16
17
18
19
21, 22
2 3, 24
30, 39
Name
nQA1, QA1
nQA0, QA0
nc
V
CCO_AB
nQB0, QB0
nPLL_BYPASS_AB
nQB1, QB1
XTAL_IN1,
XTAL_OUT1
REF_CLKC
REF_SELC
nPLL_BYPASS_C
V
CCO_C
QC0, nQC0
QC1, nQC1
V
CCA
Type
Output
Output
Unused
Power
Output
Input
Output
Input
Input
Input
Input
Power
Output
Output
Power
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
No connect.
Output supply pin for Bank A and Bank B outputs.
Differential output pair. LVPECL interface levels.
When LOW, PLL is bypassed. When HIGH, PLL output is active.
Pullup
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects
Pullup
REF_CLKC input. LVCMOS/LVTTL interface levels.
When LOW, PLL is bypassed. When HIGH, PLL output is active.
Pullup
LVCMOS/LVTTL interface levels.
Output supply pin for Bank C outputs.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pins.
Select pin. When HIGH, selects QC1/nQC1 at 155.52MHz. When LOW,
31
SELC1
Input
Pullup
selects QC1/nQC1 at 156.25MHz. LVCMOS/LVTTL interface levels.
32, 40
V
CC
Power
Core supply pins.
Output enable pin. QC1/nQC1 outputs are enable.
33
OEC1
Input
Pullup
LVCMOS/LVTTL interface levels.
Output enable pin. QC0/nQC0 outputs are enabled.
34
OEC0
Input
Pullup
LVCMOS/LVTTL interface levels.
3 5 , 43
V
EE
Power
Negative supply pins.
Select pin. When HIGH, selects QC0/nQC0 at 155.52MHz. When LOW,
36
SELC0
Input
Pullup
selects QC0/nQC0 at 156.25MHz. LVCMOS/LVTTL interface levels.
Output enable pin. QB0/nQB0, QB1/nQB1outputs are enabled.
41
OEB
Input
Pullup
LVCMOS/LVTTL interface levels.
Output enable pin. QA0/nQA0, QA1/nQA1 outputs are enabled.
42
OEA
Input
Pullup
LVCMOS/LVTTL interface levels.
45,
XTAL_OUT0,
Parallel resonant cr ystal interface. XTAL_OUT0 is the output,
Input
46
XTAL_IN0
XTAL_IN0 is the input.
47
REF_CLKAB
Input
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects
48
REF_SELAB
Input
Pullup
REF_CLKAB input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843206AGI REV. A MAY 6, 2008
ICS843206I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
59.6°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_AB
= V
CCO_C
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_AB,
V
CCO_C
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.97
V
CC
– 0.18
2.97
Typical
3.3
3.3
3.3
120
18
Maximum
3.63
V
CC
3.63
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO_AB
= V
CCO_BC
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_CLKAB, REF_CLKC
SELC0, SELC1,
nPLL_BYPASS_AB,
nPLL_BYPASS_C,
OEA, OEB, OEC0, OEC1,
REF_SELAB, REF_SELC
REF_CLKAB, REF_CLKC
SELC0, SELC1,
nPLL_BYPASS_AB,
nPLL_BYPASS_C,
OEA, OEB, OEC0, OEC1,
REF_SELAB, REF_SELC
V
CC
= V
IN
= 3.63V
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
I
IH
Input
High Current
V
CC
= V
IN
= 3.63V
5
µA
V
CC
= 3.63V, V
IN
= 0V
-5
µA
I
IL
Input
Low Current
V
CC
= 3.63V, V
IN
= 0V
-150
µA
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843206AGI REV. A MAY 6, 2008
ICS843206I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO_AB
= V
CCO_C
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1. 0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
19.44
25
50
7
Maximum
Units
MHz
MHz
Ω
pF
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO_AB
= V
CCO_C
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
Parameter
QA[0:1]/nQA[0:1]
QB[0:1]/nQB[0:1]
f
OUT
Output
Frequency
QC0/nQC0
QC1/nQC1
SELC0 = 0
SELC0 = 1
SELC1 = 0
SELC1 = 1
156.25MHz,
(1.875MHz - 20MHz)
156.25MHz,
(1.875MHz - 20MHz)
155.52MHz,
(12kHz - 1.3MHz)
20% to 80%
Test Conditions
Minimum
Typical
156.25
156.25
156.25
155.52
156.25
155.52
10
0.5
0.5
1.08
450
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
t
sk(b)
Bank Skew; NOTE 1, 2
QA[0:1]/nQA[0:1]
RMS Phase Jitter
(Random);
NOTE 3
t
jit(Ø)
QB[0:1]/nQB[0:1]
QC[0:1]/nQC[0:1]
t
R
/ t
F
Output Rise/Fall Time
odc
Output Duty Cycle
50
NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
Measured at the differential outputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: See Phase Noise plot.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843206AGI REV. A MAY 6, 2008
ICS843206I
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE AT
155.52MH
Z
➤
155.52MHz
SONET Jitter Filter
RMS Phase Jitter (Random)
12khz to 1.3MHz = 1.08ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
T
YPICAL
P
HASE
N
OISE AT
156.25MH
Z
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.5ps (typical)
➤
Gb Ethernet Jitter Filter
➤
Phase Noise Result by adding
SONET Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
5
➤
Phase Noise Result by adding
Gb Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
ICS843206AGI REV. A MAY 6, 2008
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
