Si5010
OC-12/3, STM-4/1 SONET/SDH C
LOCK AND
D
ATA
R
ECOVERY
IC
Features
Complete CDR solution includes the following:
Supports OC-12/3, STM-4/1
Low power, 293 mW (TYP OC-12)
Small footprint: 4x4 mm
DSPLL™ eliminates external loop
filter components
3.3 V tolerant control inputs
Exceeds All SONET/SDH jitter
specifications
Jitter generation
1.6 mUI
rms
(typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V supply
Ordering Information:
See page 16.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Pin Assignments
Si5010
CLKOUT+
CLKOUT–
15
RATESEL
GND
Description
The Si5010 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-12/3 or STM-4/1 data
rates. DSPLL
®
technology eliminates sensitive noise entry points thus
making the PLL less susceptible to board-level interaction and helping to
ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter,
low-power, and small size for high-speed CDRs. It operates from a single
2.5 V supply over the industrial temperature range (–40 to 85 °C).
REXT
VDD
GND
REFCLK+
REFCLK–
1
2
3
4
5
NC
20 19 18 17 16
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
GND
Pad
Connection
6
LOL
7
VDD
8
GND
9
DIN+
10
DIN–
14
13
12
11
Top View
Functional Block Diagram
LOL
DIN+
DIN–
2
BUF
DSPLL
TM
Phase-Locked
Loop
Retim er
BUF
2
DOUT+
DOUT–
PW RDN/CAL
Bias
2
BUF
2
CLKOUT+
CLKOUT–
REXT
RATESEL
REFCLK+
REFCLK–
Rev. 1.3 12/04
Copyright © 2004 by Silicon Laboratories
Si5010
Si5010
T
A B L E
Section
OF
C
O N T E N TS
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1. DSPLL
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.4. Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.6. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.7. Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.8. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Package Outline: Si5010-BM/GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 1.3
3
Si5010
1. Detailed Block Diagram
Retim e
DOUT+
DOUT–
c
DIN+
DIN–
Phase
Detector
A/D
DSP
n
VCO
CLK
Divider
CLKOUT+
c
CLKOUT–
REFCLK+
REFCLK–
Lock
Detector
LOL
RATESEL
REXT
Bias
G eneration
Calibration
PWRDN/CAL
4
Rev. 1.3
Si5010
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5010 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
2.375
Typ
25
2.5
Max
1
85
2.625
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5010 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "3. Typical Application Schematic" on page 9.
V
SIGNAL +
Differential
V
ICM
, V
OCM
SIGNAL –
I/Os
V
IS
Single Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
V
ID
,V
OD
Differential Peak-to-Peak Voltage
t
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t
C-D
DOUT
CLKOUT
Figure 2. Differential Clock to Data Timing
DOUT,
CLKOUT
t
F
t
R
80%
20%
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Rev. 1.3
5
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