700MHz, Low Jitter, Differential-to-
3.3V LVPECL Frequency Synthesizer
ICS8430-111
PRELIMINARY DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS8430-111 is a general purpose, dual out-
put high frequency synthesizer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance Clock
Solutions from IDT. The CLK, nCLK pair can accept
most standard differential input levels. The single
ended TEST_CLK input accepts LVCMOS or LVTTL input levels
and translates them to 3.3V LVPECL levels. The VCO operates at
a frequency range of 200MHz to 700MHz. With the output config-
ured to divide the VCO frequency by 2, output frequency steps as
small as 2MHz can be achieved using a 16MHz differential or
single ended reference clock. Output frequencies up to 700MHz
can be programmed using the serial or parallel interfaces to the
configuration logic. The low jitter and frequency range of the
ICS8430-111 makes it an ideal clock generator for most clock
tree applications.
F
EATURES
•
Dual differential 3.3V LVPECL output
•
Selectable 14MHz to 27MHz differential CLK, nCLK
or TEST_CLK input
•
CLK, nCLK accepts any differential input signal:
LVPECL, LVHSTL, LVDS, SSTL, HCSL
•
TEST_CLK accepts the following input types:
LVCMOS, LVTTL
•
Output frequency range up to 700MHz
•
VCO range: 200MHz to 700MHz
•
Parallel or serial interface for programming counter
and output dividers
•
Cycle-to-cycle jitter: 25ps (maximum)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
•
Industrial termperature information available upon request
IC
S
B
LOCK
D
IAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
CLK
nCLK
0
1
÷
16
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
nCLK
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8430-111
21
20
19
18
17
PLL
PHASE DETECTOR
MR
VCO
÷
M
÷
2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
CONFIGURATION
INTERFACE
LOGIC
0
÷
N
1
FOUT0
nFOUT0
FOUT1
nFOUT1
N1
N2
V
EE
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
ICS8430DY-111 REVISION F JUNE 22, 2009
1
©2009
Integrated Device Technology, Inc.
700MHz, Low Jitter, Differential-to-
3.3V LVPECL Frequency Synthesizer
F
UNCTIONAL
D
ESCRIPTION
The ICS8430-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. A16MHz clock input provides a
1MHz reference frequency. The VCO of the PLL operates over
a range of 200 to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8430-111 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
M8 and N0 through N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift regis-
ter out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fxtal x
fVCO =
2M
16
ICS8430-111
PRELIMINARY DATA SHEET
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125
≤
M
≤
350. The frequency out is defined as
follows:
fout = fVCO = fxtal x 2M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N
output divide values are latched on the HIGH-to-LOW transi-
tion of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA
input is passed directly to the M divider and N output divider on
each rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as
follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
S_LOAD
S
t
H
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
ICS8430DY-111 REVISION F JUNE 22, 2009
2
©2009
Integrated Device Technology, Inc.
700MHz, Low Jitter, Differential-to-
3.3V LVPECL Frequency Synthesizer
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3,
28, 29, 30
31, 32
4
5, 6
7
8, 16
9
10
11, 12
13
14 , 15
Name
M5, M6, M7,
M0, M1, M2,
M3, M4
M8
N0, N1
N2
V
EE
TEST
V
CC
FOUT1,
nFOUT1
V
CCO
FOUT0,
nFOUT0
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Description
ICS8430-111
PRELIMINARY DATA SHEET
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS/LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C
Function Table. LVCMOS/LVTTL interface levels.
Pullup
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
18
S_CLOCK
Input
Pulldown
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
19
S_DATA
Input
Pulldown
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
20
S_LOAD
Input
Pulldown
LVCMOS/LVTTL interface levels.
Power
Analog supply pin.
21
V
CCA
Selects between differential clock or test inputs as the PLL reference
source. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK
22
Input
Pullup
CLK_SEL
when LOW. LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
23
TEST_CLK
Input
24
CLK
Input
Pulldown Non-inver ting differential clock input.
nCLK
Input
Pullup
Inver ting differential clock input.
25
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input
Pulldown loaded into the M divider, and when data present at N2:N0 sets
the N output divider value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
27
VCO_SEL
Input
Pullup
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS8430DY-111 REVISION F JUNE 22, 2009
3
©2009
Integrated Device Technology, Inc.
700MHz, Low Jitter, Differential-to-
3.3V LVPECL Frequency Synthesizer
T
ABLE
3A. P
ARALLEL
AND
ICS8430-111
PRELIMINARY DATA SHEET
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
MR
H
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
M
X
Data
Data
X
X
X
X
N
X
Data
Data
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
Conditions
L
H
X
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
200
202
204
206
•
•
M Divide
100
101
102
103
•
•
256
M8
0
0
0
0
•
•
128
M7
0
0
0
0
•
•
64
M6
1
1
1
1
•
•
32
M5
1
1
1
1
•
•
16
M4
0
0
0
0
•
•
8
M3
0
0
0
0
•
•
4
M2
1
1
1
1
•
•
2
M1
0
0
1
1
•
•
0
0
1
1
M0
0
1
0
1
•
•
0
1
0
696
34 8
1
0
1
0
1
1
1
698
34 9
1
0
1
0
1
1
1
700
350
1
0
1
0
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to an input frequency of 16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
N2
0
0
0
0
1
1
1
1
Input
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider Value
2
4
8
16
1
2
4
8
Output Frequency (MHz)
Minimum
Maximum
100
350
50
25
12.5
200
100
50
25
175
87.5
43.75
700
350
175
87.5
ICS8430DY-111 REVISION F JUNE 22, 2009
4
©2009
Integrated Device Technology, Inc.
700MHz, Low Jitter, Differential-to-
3.3V LVPECL Frequency Synthesizer
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
ICS8430-111
PRELIMINARY DATA SHEET
Package Thermal Impedance,
θ
JA
65.7°C/W (0 mps)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply
Analog Voltage
Ouput Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3. 3
3.3
3. 3
120
10
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
M0-M7, N0, N1, MR,
S_CLOCK, S_DATA, S_LOAD,
Input
High Current TEST_CLK, nP_LOAD
M8, N2, CLK_SEL, VCO_SEL
M0-M7, N0, N1, MR,
S_CLOCK, S_DATA, S_LOAD,
Input
TEST_CLK, nP_LOAD
Low Current
M8, N2, CLK_SEL, VCO_SEL
Test Conditions
Minimum
2
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
2.6
TO
70°C
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
0.5
V
Typical
I
IL
Output
TEST; NOTE 1
High Voltage
Output
V
OL
TEST; NOTE 1
Low Voltage
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
/2.
V
OH
ICS8430DY-111 REVISION F JUNE 22, 2009
5
©2009
Integrated Device Technology, Inc.
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