DATASHEET
CLOCK RECOVERY PLL
Description
The MK1575-01 is a clock recovery Phase-Locked Loop
(PLL) designed for clock synthesis and synchronization in
cost sensitive applications. The device is optimized to
accept a low-frequency reference clock to generate a
high-frequency data or graphics pixel clock. External loop
filter components allow tailoring of loop frequency response
characteristics. For low jitter / phase noise requirements
refer to the MK2069 products.
MK1575-01
Pre-Configured Input/Output
Frequency Combinations:
Telecom T/E Clock Modes (rising edge aligned):
Addr
FS2:0
000
001
010
011
Input
Clock
8 kHz
8 kHz
8 kHz
8 kHz
Output Clocks
(MHz)
CLK1
CLK2
3.088
16.384
34.368
44.736
1.544
2.048
17.184
22.368
Clock
Type
T1
E1
E3
T3
Features
•
Long-term output jitter <2 nsec over 10
µsec
period
•
External PLL clock feedback path enable “zero delay” I/O
•
•
•
•
•
•
•
clock skew configuration
Selectable internal feedback divider provides popular
telecom and video clock frequencies (see tables below)
Can optionally use external feedback divider to generate
other output frequencies.
Single 3.3 V supply, low-power CMOS
Power-down mode and output tri-state (pin OE)
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Industrial temperature range available
Video Clock Modes (falling edge aligned):
Addr Input
FS2:0 Clock
(kHz)
100
101
110
111
15.625
15.734
15.625
15.734
Output Clocks
(MHz)
CLK1 CLK2
54
54
35.468
28.636
27
27
17.734
14.318
Clock
Type
PAL 601
NTSC 601
PAL 4xf
sc
NTSC 4xf
sc
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
The standard external clock feedback configuration is shown. Use this configuration for the pre-configured input/output
frequency combinations listed above.
C
S
C
B
R
S
CHGP
Phase Charge
Detector Pump
CHPR
Clock Input
REFIN
0
MUX
1
VCO
300 pF
VS
Divider
CLK2
Divider
CLK1
CLK2
FBIN
0
MUX
1
Divider
LUT
FCLK
Divider
FCLK
3
FS2:0
External Feedback Clock Connection
OE
IDT™
CLOCK RECOVERY PLL
1
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Pin Assignment
REFIN
FS0
VDDA
VDDD
FS1
GNDA
GNDD
CHGP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
NC
FCLK
OE
CLK2
FS2
CLK1
CHPR
16 pin 4.40 mil body, 0.65 mil pitch TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
REFIN
FS0
VDDA
VDDD
FS1
GNDA
GNDD
CHGP
CHPR
CLK1
FS2
CLK2
OE
FCLK
NC
FBIN
Pin
Type
Input
Input
Power
Power
Input
Pin Description
Reference clock input. Connect the input clock to this pin. Can be
Rising or Falling edge triggered as per Detailed Mode Selection Table,
page 3.
Frequency Selection Input bit 0, selects internal divider values as per
Detailed Mode Selection Table, page 3.
Power supply connection for internal VCO and other analog circuits.
Power supply connection for internal digital circuits and output buffers.
Frequency Selection Input bit 1, selects internal divider values as per
Detailed Mode Selection Table, page 3.
Ground Ground connection for internal VCO and other analog circuits.
Ground Ground connection for internal digital circuits and output buffers.
—
—
Output
Input
Output
Input
Output
—
Input
Loop filter connection, active node.
Loop filter connection, reference node. Do not connect to ground.
Output clock 1.
Frequency Selection Input bit 2, selects internal divider values as per
Detailed Mode Selection Table, page 3.
Output clock 2.
Output Enable, tristates CLK1, CLK2, FCLK and powers down PLL
when high. Internal pull-up.
Feedback clock output, connect to FBIN for the pre-configured
frequency combinations listed in the tables on page 1.
No internal connection, connect to ground.
Feedback clock input. Connect to CLK1, CLK2, FCLK, or the output of
an external feedback divider, depending on application. Refer to
document text for more information.
IDT™
CLOCK RECOVERY PLL
2
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Detailed Mode Selection Table
Refer to this table when not using the standard external clock feedback configuration shown on page 1.
Address
FS2:0
000
001
010
011
100
101
110
111
Internal Divider Settings
VS Divider
64
16
8
4
4
4
8
8
CLK2 Divider FCLK Divider
2
8
2
2
2
2
2
2
386
2048
4296
5592
3456
3432
2270
1820
FBIN, REFIN
Clock Edge
Rising
Rising
Rising
Rising
Falling
Falling
Falling
Falling
CLK1 Output
Frequency
Range
1.5 - 5 MHz
6 - 20 MHz
12 - 40 MHz
24 - 80 MHz
24 - 80 MHz
24 - 80 MHz
12 - 40 MHz
12 - 40 MHz
Block Diagram, Showing Device Configuration Options
C
S
C
B
R
S
CHGP
Phase Charge
Detector Pump
CHPR
Clock Input
REFIN
0
MUX
1
VCO
300 pF
VS
Divider
CLK2
Divider
CLK1
CLK2
FBIN
0
MUX
1
Divider
LUT
FCLK
Divider
FCLK
3
FS2:0
FB Divider
Optional External
Feedback Divider
OE
Feedback Clock Options
(only connect one output)
IDT™
CLOCK RECOVERY PLL
3
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Functional Description
The MK1575-01 is a PLL (phase-locked loop) based clock
generator that generates output clocks synchronized to an
input reference clock. The device can be used in the
standard configuration as described on page 1, or optionally
can use an external divider in the clock feedback path to
produce other frequency multiplication factors.
External components are used to control the PLL loop
response. The use of external loop components enables a
lower PLL loop bandwidth which is needed when accepting
low frequency input clocks such as those listed in the tables
on page 1.
clock frequency can be increased. Refer to the Output
Frequency Calculation table below.
CLK1 to FBIN
When no external feedback divider is used, this option
configures the device as a zero-delay buffer and the
frequency of CLK1 is the same as the input reference clock.
Including an external divider in the feedback path will
increase the output clock frequency. Refer to the Output
Frequency Calculation table below.
CLK2 to FBIN
Like the above configuration, this option configures the
device as a zero-delay buffer when no external feedback
divider is used, and the frequency of CLK2 is the same as
the input reference clock. Including an external divider in the
feedback path will increase the output clock frequency.
Refer to the Output Frequency Calculation table below.
PLL Clock Feedback Options
FCLK to FBIN
This is the standard configuration that is used for the
pre-configured input / output frequency combinations listed
on page 1. By including an external divider in the feedback
path (“FB Divider” in the Block Diagram of page 3) the output
Frequency and Bandwith Calculations
Feedback
Path
Option
Output Clock Frequency
CLK1
CLK2
FCLK
VCO
Frequency
f
IN
x FB x FCLK
2
x VS
“N” Factor
FCLK to
FBIN
CLK1 to
FBIN
CLK2 to
FBIN
FCLK
-
f
IN
×
FB
×
FCLK f
IN
×
FB
×
---------------
CLK2
f
IN
×
FB
----------------------
-
CLK2
f
IN
×
FB
f
IN
×
FB
---------------------
-
FCLK
CLK2
-
f
IN
×
FB
×
---------------
FCLK
VS
×
FCLK
×
FB
f
IN
×
FB
f
IN
x FB x VS
VS
×
FB
f
IN
×
FB
×
CLK2
f
IN
×
FB
f
IN
×
FB
×
CLK2
×
VS
2
VS
×
CLK2
×
FB
Notes:
1) FB = 1 when no feedback divider is used.
2) Refer to the Detail Mode Selection Table on page 3 for possible divider combinations.
3) The VCO frequency needs to be considered in all applications (see table below).
4) The external loop filter also needs to be considered.
5) Minimum VCO frequency = 96 MHz.
6) Maximum VCO frequency = 320 MHz.
7) To minimize output jitter, use the highest possible VCO frequency allowed by the application.
IDT™
CLOCK RECOVERY PLL
4
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Setting PLL Loop Bandwidth and
Damping Factor
The frequency response of the MK1575-01 PLL may be
approximated by the following equation:
factor is usually desirable. A higher damping factor will
create less passband gain peaking which will minimize the
gain of network clock wander amplitude. A higher damping
factor may also increase output clock jitter when there is
excess digital noise in the system application, due to the
reduced ability of the PLL to respond to, and therefore
compensate for, phase noise ingress.
Normalized PLL Bandwidth
=
(
R S
⋅
K O
⋅
I CP
)
----------------------------------------------
-
2π
⋅
N
Notes on setting the value of C
P
As another general rule, the following relationship should be
maintained between components C1 and C2 in the external
loop filter:
The associated damping factor is calculated as follows:
S O
CP
S
-
Damping factor,
ζ
= ------- -----------------------------------------
-
2
N
R
K
⋅
I
⋅
C
C
P
Where:
K
O
=
I
cp
=
N
=
VCO gain in Hz/Volt
(use 340 MHz/V)
Charge pump current, 12.5
µA
Total feedback divide from VCO,
(Refer to N Value table, below)
External loop filter capacitor in Farads
Where:
= ------
20
C
S
C
P
=
C
B
+ 300 pF
C
B
= External bypass capacitor in Farads
Note that the MK1575-01 contains an internal 300 pF filter
cap which is connected in parallel with external device C
B
.
This helps to reduce output clock jitter. In some applications
external device C
B
will not be required.
C
P
establishes a second pole in the PLL loop filter. For
higher damping factors (>1), calculate the value of C
P
based
on a C
S
value that would be used for a damping factor of 1.
This will minimize baseband peaking and loop instability that
can lead to output jitter.
C
P
also helps to damp VCO input voltage modulation
caused by the charge pump correction pulses. A C
P
value
that is too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme cases
where input jitter is high, charge pump current is high, and
C
P
is too small, the VCO input voltage can hit the supply or
ground rail resulting in non-linear loop response.
The best way to set the value of C
P
is to use the External
Loop Filter Solver located on the IDT web site.
C
S
=
R
S
= Loop filter resistor in Ohms
The above bandwidth equation calculates the “normalized”
loop bandwidth which is approximately equal to the - 3dB
bandwidth. This approximate calculation does not take into
account the effects of damping factor or the third pole
imposed by C
P
. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on the output clocks due to modulation of
the PLL by the input reference frequency, the following
general rule should be observed:
f
Phase Detector
PLL Bandwidth
≤
--------------------------------
20
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. For video applications, a low
damping factor (0.7 to 1.0) is generally desired for fast
genlocking. For telecom applications, a higher damping
IDT™
CLOCK RECOVERY PLL
5
MK1575-01
REV N 121809
嵌入式系统
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