ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87158 is a high performance 1-to-6 LVPECL-to-
HCSL/LVCMOS ClockGenerator. The ICS87158 has one
differential input (which can accept LVDS, LVPECL, LVHSTL,
SSTL, HCSL), six differential HCSL output pairs and two
complementary LVCMOS/LVTTLoutputs. The six HCSL
output pairs can be individually configured for divide-by-1, 2,
and 4 or high impedance by use of select pins. The two
complementary LVCMOS/LVTTL outputs can be configured
for divide by 2, divide by 4, high impedance, or driven low for
low power operation.
The primary use of the ICS87158 is in Intel
®
E8870 chipsets
that use Intel
®
Pentium 4 processors. The ICS87158 converts
the differential clock from the main system clock into HCSL
clocks used by Intel
®
Pentium 4 processors. However, the
ICS87158 is a highly flexible, general purpose device that
operates up to 600MHz and can be used in any situation where
Differential-to-HCSL translation is required.
F
EATURES
•
Six HCSL outputs
•
Two LVCMOS/LVTTL outputs
•
One Differential LVPECL clock input pair
•
PCLK, nPCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 600MHz (maximum)
•
Output skew: 100ps (maximum)
•
Propagation delay: 4ns (maximum)
•
3.3V operating supply
•
0°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
•
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
MULT_0
MULT_1
IREF
▲
P
IN
A
SSIGNMENT
GND
V
DD
V
DD
_R
PCLK
nPCLK
GND_R
V
DD
_M
MREF
nMREF
GND_M
V
DD
GND
V
DD
_L
V
DD
GND_L
SEL_T
MULT_0
MULT_1
V
DD
_L
GND_L
SEL_A
SEL_B
SEL_U
PWR_DWN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
GND_H
V
DD
_H
HOST_P1
HOST_N1
GND_H
HOST_P2
HOST_N2
V
DD
_H
HOST_P3
HOST_N3
GND_H
HOST_P4
HOST_N4
V
DD
_H
HOST_P5
HOST_N5
GND_H
HOST_P6
HOST_N6
V
DD
_H
IREF
GND_I
V
DD
_I
CURRENT
ADJUST
-
+
÷1,2,4
PWR_DWN#
SEL_T
V
DD
HOST_P1
HOST_N1
GND_H
V
DD
HOST_P6
HOST_N6
GND_H
V
DD
HOST_P2
HOST_N2
GND_H
V
DD
HOST_P3
HOST_N3
GND_H
V
DD
HOST_P4
HOST_N4
GND_H
V
DD
HOST_P5
HOST_N5
GND_H
V
DD
MREF
nMREF
GND_H
PCLK
nPCLK
÷1,2,4
SEL_A
SEL_B
SEL_U
DIVIDER
CONTROL
48-Lead TSSOP
6.1mm x 12.5mm x .92mm body package
G Package
Top View
48-Lead SSOP
7.5mm x 15.9mm x 2.3mm body package
F Package
Top View
÷2,4
87158AG
www.idt.com
1
REV. C JULY 25, 2010
ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 12
2, 11, 14, 48
3
4
5
6
7
8, 9
10
13
15, 20
16
17
Name
GND
V
DD
V
DD
_R
PCLK
nPCLK
GND_R
V
DD
_M
MREF,
nMREF
GND_M
V
DD
_L
GND_L
SEL_T
MULT_0
Type
Power
Power
Power
Input
Input
Power
Power
Output
Power
Power
Power
Input
Input
Description
Power supply ground.
Positive supply pins.
Power supply pin for differential reference clock inputs.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Power supply ground for differential inputs.
Power supply pin for MREF clock outputs.
Single ended clocks provided as a reference clock to a
memor y clock driver. LVCMOS / LVTTL interface levels.
Power supply ground for MREF clock outputs.
Power supply pin for logic input pins.
Power supply ground for logic input pins.
Active high input tristates all outputs.
Pulldown
LVCMOS / LVTTL interface levels.
The logic setting on these two pins selects the multiplying factor
Pulldown of the IREF reference current for the HOST pair outputs.
LVCMOS / LVTTL interface levels.
The logic setting on these two pins selects the multiplying factor
Pullup
of the IREF reference current for the HOST pair outputs.
LVCMOS / LVTTL interface levels.
Power supply pin for logic input pins.
Pulldown
Selects desired output frequencies.
LVCMOS / LVTTL interface levels.
Asynchronous active-low LVTTL power-down signal forces MREF
outputs low, tristates HOST_N outputs, and drives HOST_P output
currents to 2xIREF. LVCMOS / LVTTL interface levels.
Power supply pin for IREF current reference input.
Power supply ground for IREF current reference input.
A fixed precision resistor from this pin to ground provides a reference
current used for differential current-mode HOST clock outputs.
Power supply pins for the differential HOST clock outputs.
Differential output pairs. HCSL interface levels.
18
19
21, 22, 23
MULT_1
V
DD
_L
SEL_A,
SEL_B,
SEL_U
PWR_DWN#
V
DD
_I
GND_I
IREF
V
DD
_H
HOST_N6,
HOST_P6
Input
Power
Input
24
25
26
27
28, 34, 40, 46
29, 30
31, 37, 43, 47
Input
Power
Power
Input
Power
Output
Pullup
GND_H
Power
Power supply ground for the differential HOST clock outputs.
HOST_N5,
32, 33
Output
Differential output pairs. HCSL interface levels.
HOST_P5
HOST_N4,
Differential output pairs. HCSL interface levels.
35, 36
Output
HOST_P4
HOST_N3,
38, 39
Output
Differential output pairs. HCSL interface levels.
HOST_P3
HOST_N2,
41, 42
Output
Differential output pairs. HCSL interface levels.
HOST_P2
HOST_N1,
Differential output pairs. HCSL interface levels.
44, 45
Output
HOST_P1
NOTE:
Pullup
and
Puddown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87158AG
www.idt.com
2
REV. C JULY 25, 2010
ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
PWR
_DWN#
1
1
1
1
1
1
1
1
1
0
Inputs
SEL SEL
_T
_A
0
0
0
0
0
0
0
0
0
1
X
0
0
0
1
1
1
1
X
X
SEL
_B
0
0
1
1
0
0
1
1
X
X
SEL
_U
0
1
0
1
0
1
0
1
X
X
HST_P1
HST_N1
÷2
Hi Z
÷4
÷4
÷1
Hi Z
÷2
÷2
Hi Z
HST_P1
=2 x IREF
HST_N1
= Hi Z
HST_P2
HST_N2
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
HST_P2
=2 x IREF
HST_N2
= Hi Z
HST_P3
HST_N3
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
HST_P3
=2 x IREF
HST_N3
= Hi Z
Outputs
HST_P4
HST_N4
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
HST_P4
=2 x IREF
HST_N4
= Hi Z
HST_P5
HST_N5
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
HST_P5
=2 x IREF
HST_N5
= Hi Z
HST_P6
HST_N6
÷2
Hi Z
÷4
÷4
÷1
Hi Z
÷2
÷2
Hi Z
HST_P6
=2 x IREF
HST_N6
= Hi Z
MREF_P
MREF_N
÷4
÷4
÷4
÷4
÷4
÷4
÷4
÷2
Hi Z
MREF_P
= low
MREF_N
= low
T
ABLE
3B. F
UNCTION
T
ABLE
Inputs
MULT_0
0
0
1
1
MULT_1
0
1
0
1
Board Target
Trace/Term Z
50
Ω
50
Ω
50
Ω
50
Ω
Device Configurations
Reference R,
IREF = V
DD
/ (3*Rr)
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Output Current
I
OH
= 5*IREF
I
OH
= 6*IREF
I
OH
= 4*IREF
I
OH
= 7*IREF
V
OH
@ 50
Ω
Environment
0.6V
0.7V
0.5V
0.8V
87158AG
www.idt.com
3
REV. C JULY 25, 2010
ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
48 Lead TSSOP
48 Lead SSOP
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
58.3°C/W (0 lfpm)
52.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
65
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
MULT_1, PWR_DWN#
Input High Current SEL_A, SEL_B,
SEL_T, SEL_U,
MULT_0
MULT_1, PWR_DWN#
Input Low Current SEL_A, SEL_B,
SEL_T, SEL_U
MULT_0
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
mV
mV
µA
µA
µA
µA
V
V
I
IL
V
OH
Output Low Voltage; NOTE 1
V
OL
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Paramter Measurement Information Section,
"3.3V Output Load Test Circuit".
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK, nPCLK
PCLK, nPCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
Units
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
CMR
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
87158AG
www.idt.com
4
REV. C JULY 25, 2010
ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
T
ABLE
4D. HCSL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
I
OH
V
OH
V
OL
I
OZ
V
OX
Parameter
Output Current
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Crossover Voltage
RREF = 475
Ω
, RLOAD = 50
Ω
I
OH
= 6*IREF
RREF = 475
Ω
, RLOAD = 50
Ω
I
OH
= 6*IREF
-10
280
Test Conditions
Minimum
12.9
0.7
0.03
10
430
Typical
Maximum
14.9
Units
mA
V
V
µA
mV
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
T
ABLE
5A. HCSL AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4, 5
Par t-to-Par t Skew; NOTE 3, 5
Cycle-to-Cycle Jitter
Output Rise Time
Output Fall Time
20% to 80%
20% to 80%
175
175
3.7
60
Test Conditions
Minimum
Typical
Maximum
600
4.0
100
500
150
700
700
Units
MHz
ns
ps
ps
ps
ps
ps
t
sk(o)
t
sk(pp)
t
jit(cc)
t
R
t
F
odc
Output Duty Cycle
48
52
%
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: Maximum value calculated at +3
σ
from typical.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. LVCMOS / LVTTL AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
f
MAX
Parameter
Output Frequency
Cycle-to-Cycle Jitter
Output Rise Time
Output Fall Time
C
L
= 10pF/30pF
0.4V to 2.4V, C
L
= 10pF
0.4V to 2.4V, C
L
= 30pF
0.4V to 2.4V, C
L
= 10pF
0.4V to 2.4V, C
L
= 30pF
0.4
2
52
0.4
1.8
Test Conditions
Minimum
Typical
Maximum
300
150
Units
MHz
ps
ns
ns
ns
ns
%
t
jit(cc)
t
R
t
F
o dc
Output Duty Cycle
C
L
= 10pF/30pF
48
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to MREF outputs only.
www.idt.com
5
87158AG
REV. C JULY 25, 2010
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