FemtoClocks™ Crystal-to-LVCMOS/
LVTTL Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 840002I is a 2 output LVCMOS/LVTTL Synthesizer
optimized to generate Fibre Channel reference clock
frequencies. Using a 26.5625MHz 18pF parallel resonant
crystal, the following frequencies can be generated based on the
2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz,
156.25MHz, 106.25MHz, and 53.125MHz. The 840002I uses
IDT’s 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Fibre Channel jitter requirements. The 840002I is packaged in
a 16-pin TSSOP package.
840002I
DATASHEET
F
EATURES
• Two LVCMOS outputs @ 3.3V, 17Ω typical output imped-
ance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Output frequency range: 46.66MHz - 233.33MHz
• VCO range: 560MHz - 700MHz
• Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• RMS phase jitter @ 212.5MHz (637KHz - 10MHz):
0.83ps (typical)
Typical phase noise at 212.5MHz:
Offset
Noise Power
100Hz ................-91.3 dBc/Hz
1KHz ..............-114.3 dBc/Hz
10KHz ..............-120.7 dBc/Hz
100KHz ..............-120.2 dBc/Hz
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
Inputs
Output Frequency
(MHz)
212.5
159.375
106.25
53.125
156.25
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
F_SEL1
0
0
1
1
0
F_SEL0
0
1
0
1
1
M Divider Value
24
24
24
24
24
N Divider Value
3
4
6
12
4
M/N Ratio Value
8
6
4
2
6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
DDO
XTAL_IN
XTAL_OUT
840002I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
840002I REVISION A 3/30/15
1
©2015 Integrated Device Technology, Inc.
840002I DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1,
16
2
3
4
5
Name
F_SEL0, F_
SEL1
nXTAL_SEL
TEST_CLK
OE
MR
Input
Input
Input
Input
Input
Type
Pullup
Description
Frequency select pins. LVCMOS/LVTTL interface levels.
Selects between the crystal or TEST_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Pulldown Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing active outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
Pulldown
clock frequency/n output divider.
LVCMOS/LVTTL interface levels.
Pullup
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Output supply pin.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
6
7
8
9,
10
11
12, 13
14, 15
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
V
DDO
Q1, Q0
GND
Input
Power
Power
Input
Power
Output
Power
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
3.3V±5%
2.5V±5%
14
16
Test Conditions
Minimum
Typical
4
8
51
51
17
21
21
25
Maximum
Units
pF
pF
kΩ
kΩ
Ω
Ω
T
ABLE
3. F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
Inputs
M Divider Value N Divider Value
24
3
24
24
24
24
4
6
12
4
Output Frequency
(MHz)
212.5
159.375
106.25
53.125
156.25
F_SEL1
0
0
1
1
0
F_SEL0
0
1
0
1
1
M/N Divider Value
8
6
4
2
6
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
2
REVISION A 3/30/15
840002I DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
2.375
Typical
3.3
3.3
3.3
2.5
Maximum
3.465
3.465
3.465
2.625
100
12
5
Units
V
V
V
V
mA
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
95
12
5
Units
V
V
V
mA
mA
mA
REVISION A 3/30/15
3
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
840002I DATA SHEET
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%
OR
2.5V±5%,
OR
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
OE
F_SEL0:1, nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
OE
F_SEL0:1, nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
V
DDO
= 3.3V or 2.5V±5%
-150
-5
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
I
IH
Input
High Current
I
IL
Input
Low Current
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuit.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
26.5625
50
7
Maximum
Units
MHz
Ω
pF
Fundamental
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
4
REVISION A 3/30/15
840002I DATA SHEET
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 3
212.5MHz @ Integration Range:
637KHz - 10MHz
159.375MHz @ Integration Range:
637KHz - 10MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
106.25MHz @ Integration Range:
637KHz - 10MHz
53.125MHz @ Integration Range:
637KHz - 10MHz
20% to 80%
F_SEL[1:0] 00
F_SEL[1:0] = 00
200
46
42
0.83
0.62
0.59
0.80
0.68
700
54
58
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.67
170
113.33
56.67
12
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 3
212.5MHz @ Integration Range:
637KHz - 10MHz
159.375MHz @ Integration Range:
637KHz - 10MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
106.25MHz @ Integration Range:
637KHz - 10MHz
53.125MHz @ Integration Range:
637KHz - 10MHz
20% to 80%
F_SEL[1:0] 00
F_SEL[1:0] = 00
200
46
42
0.73
0.62
0.56
0.76
0.72
700
54
58
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.67
170
113.33
56.67
12
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
REVISION A 3/30/15
5
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/
LVTTL FREQUENCY SYNTHESIZER
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