a
FEATURES
Very Low Noise 5nV/
÷
Hz
@ 1 kHz Max
Excellent Input Offset Voltage 75 V Max
Low Offset Voltage Drift 1 V/ C Max
Very High Gain 1500 V/ V Min
Outstanding CMR 106 dB Min
Slew Rate 2.4V/ms Typ
Gain-Bandwidth Product 5 Hz Typ
Industry Standard 8-Lead Dual Pinout
GENERAL DESCRIPTION
Dual Very Low Noise Precision
Operational Amplifier
OP270
CONNECTION DIAGRAMS
16-LEAD SOL
(S-Suffix)
–IN A
1
+IN A
2
NC
3
V–
4
NC
5
+IN B
6
–IN B
7
NC
8
16
OUT A
15
NC
14
NC
13
V+
12
NC
11
NC
10
OUT B
9
NC
EPOXY MINI-DIP (P-Suffix)
8-LEAD HERMETIC DIP
(Z”Suffix)
OUT A
1
–IN A
2
+IN A
3
V–
4
A
B
8
V+
7
OUT B
6
–IN B
5
+IN B
The OP270 is a high-performance monolithic dual operational
amplifier with exceptionally low voltage noise, 5n÷Hz at 1kHz Max,
offering comparable performance to ADI’s industry standard OP27.
The OP270 features an input offset voltage below 75
mV
and an
offset drift under 1
mV/∞C,
guaranteed over the full military tempera-
ture range. Open-loop gain of the OP270 is over 1,500,000 into a
10 kW load insuring excellent gain accuracy and linearity, even in
high-gain applications. Input bias current is under 20 nA which
reduces errors due to signal source resistance. The OP270’s CMR of
over 106 dB and PSRR of less than 3.2
mV/V
significantly reduce
errors due to ground noise and power supply fluctuations. Power
consumption of the dual OP270 is one-third less than two OP27s,
a significant advantage for power conscious applications. The
OP270 is unity-gain stable with a gain bandwidth product of 5 MHz
and a slew rate of 2.4 V/ms.
NC = NO CONNECT
The OP270 offers excellent amplifier matching which is important
for applications such as multiple gain blocks, low noise instrumen-
tation amplifiers, dual buffers, and low-noise active filters.
The OP270 conforms to the industry standard 8-lead DIP pinout. It
is pin-compatible with the MC1458, SE5532/A, RM4558, and
HA5102 dual op amps, and can be used to upgrade systems using
these devices.
For higher speed applications the OP271, with a slew rate of 8 V/ms, is
recommended. For a quad op amp, see the OP470.
FUNCTIONAL BLOCK DIAGRAM
(One of Two Amplifiers Is Shown)
V+
BIAS
OUT
–IN
+IN
V–
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP270–SPECIFICATIONS
(
PARAMETER
SYMBOL
Vs =
15 V,
T
A
=
25 C, unless otherwise noted.
)
CONDITIONS
OP270A/E
MIN TYP MAX
OP270F
MIN TYP MAX
MIN
OP270G
TYP MAX UNIT
Input Offset Voltage
Input OffsetCurrent
Input BiasCurrent
Input Noise Voltage
Input Noise
Voltage Density
Input Noise
Current Density
Large-Signal
Voltage Gain
V
OS
l
OS
I
B
e
n
p-p
e
n
i
n
A
vo
Input Voltage Range IVR
Output Voltage Swing V
O
Common-Mode
Rejection
CMR
Power Supply
Rejection Ratio
PSRR
Slew Rate
Supply Current
(All Amplifiers)
Gain Bandwidth
Channel Separation
SR
I
SY
GBW
Product
CS
V
CM
= 0 V
V
CM
= 0 V
0.1 Hz to 10 Hz
f
O
= 10 Hz
f
O
= 100 Hz
f
O
= 1 kHz
(Note 2)
f
O
= 10 Hz
f
O
= 100 Hz
f
O
= 1 kHz
V
O
=
±
10 V
R
L
= 10 kW
R
L
= 2 kW
(Note3)
R
L
≥
2 kW
V
CM
=
±
11 V
V
S
=
±
4.5 V
to
±
18 V
No Load
10
1
5
80
3.6
3.2
3.2
1.1
0.7
0.6
1500
750
+12
+12
106
75
10
20
200
6.5
5.5
5.0
20
3
10
80
3.6
3.2
3.2
1.1
0.7
0.6
1000
500
±
12
±
12
100
1700
900
+12.5
+13.5
120
1.0
1.7
2.4
4
5
150
15
40
200
6.5
5.5
5.0
50
5
15
80
3.6
3.2
3.2
1.1
0.7
0.6
750
1500
350
700
±
12
±
12.5
+12
±
13.5
90
110
1.5
1.7
2.4
4
5
250
20
60
mV
nA
nA
nV p-p
nV
÷
Hz
pA
÷
Hz
2300
1200
±
12.5
±
13.5
125
0.56 3.2
V/mV
V
V
dB
6
mV/V
V/ms
mA
MHz
5.6
1.7
2.4
4
5
6.5
6.5
6.5
V
O
=
±
20 V P-P
f
O
= 10 Hz
(Note 1)
125
175
3
04
20
125
175
3
0.4
20
5
175
3
0.4
20
5
dB
PF
MW
GW
ms
Input Capacitance
Input Resistance
Differential-Mode
Input Resistance
Common-Mode
SettlingTime
C
IN
R
IN
R
INCM
t
S
AV = + t, 10 V
Step to 0.01%
5
NOTES
1. Guaranteed by not 100% tested.
2. Sample tested.
3. Guaranteed by CMR test.
Specifications subject to change without notice.
–2–
REV. B
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
(
PARAMETER
SYMBOL
CONDITIONS
OP270
Vs =
15 V, –40∞C
£
T
A
£
85 C, unless otherwise noted.
)
OP270E
MIN TYP MAX
OP270F
MIN TYP MAX
OP270G
MIN TYP MAX UNIT
A
VO
R
L
= 2 kW
Input Voltage Range* IVR
Output Voltage Swing V
O
Common-Mode
Rejection
CMR
Power Supply
Rejection Ratio
PSRR
Supply Current
(All Amplifiers)
*
Guaranteed by CMR test.
Input Offset Voltage
Average Input
Offset Voltage Drift
Input Offset Current
Input Bias Voltage
Large-Signal
Voltage Gain
V
OS
TCV
OS
I
OS
I
B
V
CM
= 0 V
V
CM
= 0 V
V
O
=
±
10 V
R
L
= 10 kW
R
L
≥
2 kW
V
CM
=
±
11 V
V
S
=
±
4.5 V
to
±
18 V
No Load
25
0.2
1.5
6
1000
500
+12
+12
100
150
1
30
60
600
300
±
12
±
12
94
5.6
7.2
45
0.4
5
15
1400
700
+12.5
+13.5
115
1.8
4.4
275
2
40
70
400
225
±
12
±
12
90
10
7.2
100
0.7
15
19
1250
670
400
3
50
80
mV
mV/∞C
nA
nA
V/mV
1800
900
±
12.5
±
13.5
120
0.7
4.4
±
12.5 V
±
13.5 V
dB
1.5
7.2
mV/V
mA
100
2.0
4.4
I
SY
Specifications subject to change without notice.
ELECTRICAL SPECIFICATIONS
(
PARAMETER
SYMBOL
CONDITIONS
Vs =
15 V, –55∞C
£
T
A
£
125 C for OP270A, unless otherwise noted.
)
MIN
OP270A
TYP
MAX
UNIT
Input Offset Voltage
Average Input
Offset Voltage Drift
Input Offset Current
Input Bias Voltage
Large-Signal
Voltage Gain
Input Voltage Range*
Output Voltage Swing
Common-Mode
Rejection
Power Supply
Rejection Ratio
Supply Current
(All Amplifiers)
*
Guaranteed by CMR test.
V
OS
TCV
OS
I
OS
I
B
A
VO
IVR
V
O
CMR
PSSR
I
SY
V
CM
= 0 V
V
CM
= 0 V
V
O
=
±
10
R
L
= 10 kW
R
L
= 2 kW
R
L
≥
2 kW
V
CM
=
±
11 V
V
s
=
±
4.5 V
to
±
18 V
No Load
30
0.1
2
6
750
400
±
12
±
12
100
1600
800
±
12.5
±
13
120
1.0
4.5
175
1
30
60
mV
mV/∞C
nA
nA
V/mV
V
V
dB
5.6
7.5
mV/V
mA
Specifications subject to change without notice.
REV. B
–3–
OP270–SPECIFICATIONS
WAFER LIMITS
(
PARAMETER
Input OffsetVoltage
Input OffsetCurrent
Input Bias Current
Large-Signal A
vo
Voltage Gain
Input VoltageRange
Output Voltage Swing
Common-ModeRejection
Power Supply
Rejection Ratio
Supply Current
(All Amplifiers)
Vs =
15 V,
T
A
=
25∞C, unless otherwise noted.
)
SYMBOL
Vos
los
IB
CONDITIONS
VCM = 0 V
VCM = 0 V
Vo =
±
10 V
RL = 2 kW
(Note1)
R
L
≥
2 2 kW
V
CM
=
±
12V
V
S
=
±
4.5 V to
±
1 8 V
No Load
LIMIT
150
15
40
500
±
12
±
12
100
5.6
6.5
TYP
mV
MAX
nA MAX
nA MAX
V/mV MIN
V MIN
V MIN
dB MIN
mV/V
MAX
mA MAX
IVR
V
O
CMR
PSRR
ISY
NOTE:
1.Guaranteed by CMR test. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yields loss, yield
afler packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot
assembly and testing.
Specifications subject to change without notice.
DICE CHARACTERISTICS
1. OUT A
2. -IN A
3. +INA
4. V-
5. +IN B
6. -IN B=
7. OUT B
8. V+
DIE SIZE 0.094 x 0.092 inch, 8,648 sq. mils
(2.39 x 2.34 mm, 5.60 sq. mm)
Substrate is internally connected to V-
–4–
REV. B
SPECIFICATIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . .
±
1.0 V
Differential Input Current
2
. . . . . . . . . . . . . . . . . . . .
±
25 mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . Continuous
Storage Temperature Range
P, S. Z-Package . . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
Junction Temperature (T
J
) . . . . . . . . . . . . . –45∞C to +150∞C
Operating Temperature change
OP270A . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
OP270E, OP270F, OP270G . . . . . . . . . . . . . . 40∞C to +85∞C
ABSOLUTE MAXIMUM RATINGS
1
OP270
NOTES:
1
Absolute maximum ratings apply to both DICE and packaged pans,
unless otherwise noted.
2
The OP270’s inputs are protected by back-to-back diodes.
Current limiting resistors are not used in order to achieve low noise
performance. lf differential voltage exceeds +10 V, the input current
should be limited to
±
25 mA.
ORDERING GUIDE
Model
OP270AZ
1
OP270EZ
OP270FZ
OP270GP
OP270GS
1
2
TA = +25 V
V
OS
MAX
( V)
75
75
150
250
250
q
JC
12
12
12
37
27
2
q
JA
2
Temperature Package
Package
Range ( C)
Description Option
MIL
XIND
XIND
XIND
XIND
Cerdip
Cerdip
Cerdip
Plastic
Plastic
8-Lead HermeticDIP(Z)
8-Lead HermeticDIP(Z)
8-Lead HermeticDIP(Z)
8-Lead Plastic DIP (P)
16-Lead SOL (S)
Unit
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
134
134
134
96
92
Not for new design, obsolete April 2002
qJA
is specified for worst-case mounting conditions, i.e.,
qJA
is specified
for device in socket for Cerdip and P-DIP packages;
qJA
is specified for
device soldered to printed circuit board for SOL package.
For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number
5962-88721012A
*
5962-8872101PA
*
Not
ADI Equivalent
OP270ARCMDA
OP270AZMDA
for new designs; obsolete April 2002.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP270 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
