DATA SHEET
Integrated
350MHZ, CRYSTAL-TO-LVCMOS/
Circuit
Systems, Inc.
LVTTL FREQUENCY SYNTHESIZER
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
F
EATURES
•
2 LVCMOS/LVTTL outputs
•
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
•
Output frequency range: 15.625MHz to 350MHz
•
Crystal input frequency range: 12MHz to 40MHz
•
VCO range: 250MHz to 700MHz
•
Parallel or serial interface for programming counter
and output dividers
•
RMS period jitter: 8ps (typical)
•
Cycle-to-cycle jitter: 40ps (typical)
•
Full 3.3V or mixed 3.3V core/2.5V output supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
ICS8402
ICS8402
G
ENERAL
D
ESCRIPTION
The ICS8402 is a general purpose, Crystal-to-
LVCMOS/LVTTL High Frequency Synthesizer and
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8402 has a selectable TEST_CLK or crystal
inputs. The VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The low
phase noise characteristics of the ICS8402 make it an ideal
clock source for Gigabit Ethernet and SONET applications.
IC
S
B
LOCK
D
IAGRAM
OE0
OE1
VCO_SEL
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
M4
32 31 30 29 28 27 26 25
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
1
0
M5
M6
M7
M8
N0
N1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VCO
÷
M
0
1
÷2
÷4
÷8
÷16
TEST
V
DD
OE1
OE0
V
DDO
Q1
Q0
GND
M3
ICS8402
M2
M1
M0
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
nc
GND
Q0
Q1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.75mm package body
K Package
Top View
8402AY
www.icst.com/products/hiperclocks.html
1
REV. C SEPTEMBER 1, 2005
IDT™ / ICS™
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
1
ICS8402
Integrated
ICS8402
Circuit
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8402
F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the
Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8402 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of
the LVCMOS output buffers. The divider provides a 50% out-
put duty cycle.
The programmable features of the ICS8402 support two in-
put modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on in-
puts M0 through M8 and N0 and N1 is passed directly to the
M divider and N output divider. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N out-
put divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when op-
erating in the parallel input mode. The relationship between
the VCO frequency, the crystal frequency and the M divider
is defined as follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10
≤
M
≤
28. The frequency
out is defined as follows: FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The con-
tents of the shift register are loaded into the M divider and N
output divider when S_LOAD transitions from LOW-to-HIGH.
The M divide and N output divide values are latched on the
HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
Shift Register Output
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
8402AY
www.icst.com/products/hiperclocks.html
2
REV. C SEPTEMBER 1, 2005
IDT™ / ICS™
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
2
ICS8402
Integrated
ICS8402
Circuit
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8402
F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
1 4, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
GND
TEST
V
DD
OE1, OE0
V
DDO
Q1, Q0
Input
Input
Input
Unused
Power
Output
Power
Input
Power
Output
Pullup
Type
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition
Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
No connect.
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
Core supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3D,
OE Function Table. LVCMOS / LVTTL interface levels.
Output supply pin.
Clock outputs. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
internal dividers and the outputs are enabled. Asser tion of MR
does not effect loaded M, N, and T values.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels
Description
17
MR
Input
Pulldown
18
19
20
21
22
23
24, 25
26
27
S_CLOCK
S_DATA
S_LOAD
V
DDA
XTAL_SEL
TEST_CLK
XTAL_OUT,
XTAL_IN
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8402AY
www.icst.com/products/hiperclocks.html
3
REV. C SEPTEMBER 1, 2005
IDT™ / ICS™
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
3
ICS8402
Integrated
ICS8402
Circuit
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8402
F
REQUENCY
S
YNTHESIZER
Typical
4
13
11
51
51
Maximum
Units
pF
pF
pF
kΩ
kΩ
12
Ω
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
V
DD
, V
DDA
, V
DDO
= 3.465V
V
DD
, V
DDA
= 3.465V, V
DDO
= 2.625V
Test Conditions
Minimum
7
T
ABLE
3A. P
ARALLEL AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
Conditions
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
8402AY
www.icst.com/products/hiperclocks.html
4
REV. C SEPTEMBER 1, 2005
IDT™ / ICS™
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
4
ICS8402
Integrated
ICS8402
Circuit
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8402
F
REQUENCY
S
YNTHESIZER
8
4
M2
0
0
•
•
0
0
1
2
M1
1
1
•
•
1
1
0
1
M0
0
1
•
•
0
1
0
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
275
•
•
650
675
700
M Divide
10
11
•
•
26
27
28
256
M8
0
0
•
•
0
0
0
128
M7
0
0
•
•
0
0
0
64
M6
0
0
•
•
0
0
0
32
M5
0
0
•
•
0
0
0
16
M4
0
0
•
•
1
1
1
M3
1
1
•
•
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
2
4
8
16
N Divider Value
Output Frequency
(MHz)
Minimum Maximum
125
62.5
31.25
15.625
350
175
87.5
43.75
T
ABLE
3D. O
UTPUT
E
NABLE
& C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Control Inputs
OE0
0
0
1
1
OE1
0
1
0
1
Q0
Hi-Z
Hi-Z
Enabled
Enabled
Output
Q1
Hi-Z
Enabled
Hi-Z
Enabled
8402AY
www.icst.com/products/hiperclocks.html
5
REV. C SEPTEMBER 1, 2005
IDT™ / ICS™
350MHZ, CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER
5
ICS8402
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