19-4858; Rev 0; 8/09
EVALUATION KIT AVAILABLE
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
General Description
The MAX3679A is a low-jitter precision clock generator
with the integration of three LVPECL and one LVCMOS
outputs optimized for Ethernet applications. The device
integrates a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet applications.
This proprietary PLL design features ultra-low jitter
(0.36psRMS) and excellent power-supply noise rejection,
minimizing design risk for network equipment.
Features
♦
Crystal Oscillator Interface: 25MHz
♦
CMOS Input: 25MHz
♦
Output Frequencies for Ethernet
62.5MHz, 125MHz, 156.25MHz, 312.5MHz
♦
Low Jitter
0.14ps
RMS
(1.875MHz to 20MHz)
0.36ps
RMS
(12kHz to 20MHz)
♦
Excellent Power-Supply Noise Rejection
♦
No External Loop Filter Capacitor Required
MAX3679A
Applications
Ethernet Networking Equipment
Ordering Information
PART
MAX3679AETJ+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFN-EP*
Pin Configuration appears at end of data sheet.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Typical Application Circuit
+3.3V
±5%
10.5Ω
0.1μF
0.1μF
0.1μF
0.01μF
0.1μF
10μF
V
CC
V
CCA
0.1μF
MR
REF_IN
IN_SEL
QAC_OE
QA_OE
QB0_OE
V
CC
QB1_OE
BYPASS
SELA1
SELA0
SELB1
SELB0
RES1
RES0
X_OUT
V
CCO_A
V
CCO_B
V
DDO_A
QA_C
125MHz
QA
QA
125MHz
36Ω
Z
0
= 50Ω
ASIC
Z
0
= 50Ω
Z
0
= 50Ω
50Ω
50Ω
ASIC
(V
CC
- 2V)
MAX3679A
QB0
QB0
312.5MHz
Z
0
= 50Ω
Z
0
= 50Ω
50Ω
50Ω
ASIC
(V
CC
- 2V)
QB1
QB1
X_IN
GND
GNDO_A
312.5MHz
50Ω
50Ω
(V
CC
- 2V)
Z
0
= 50Ω
Z
0
= 50Ω
ASIC
25MHz
(C
L
= 18pF)
33pF
27pF
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
MAX3679A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range V
CC
, V
CCA
,
V
DDO_A
, V
CCO_A
, V
CCO_B
................................-0.3V to +4.0V
Voltage Range at REF_IN, IN_SEL,
SELA[1:0], SELB[1:0], RES[1:0],
QAC_OE, QA_OE, QB0_OE, QB1_OE,
MR,
BYPASS
..........................................-0.3V to (V
CC
+ 0.3V)
Voltage Range at X_IN Pin ...................................-0.3V to +1.2V
Voltage Range at GNDO_A...................................-0.3V to +0.3V
Voltage Range at X_OUT ............................-0.3V to (V
CC
- 0.6V)
Current into QA_C ...........................................................±50mA
Current into QA,
QA,
QB0,
QB0,
QB1,
QB1
.....................-56mA
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
PARAMETER
Power-Supply Current
SYMBOL
I
CC
(Note 4)
CONDITIONS
MIN
TYP
77
MAX
100
UNITS
mA
CONTROL INPUT CHARACTERISTICS
(SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR,
BYPASS
Pins)
Input Capacitance
Input Pulldown Resistor
Input Logic Bias Resistor
Input Pullup Resistor
C
IN
R
PULLDOWN
Pin MR
R
BIAS
R
PULLUP
Pins SELA[1:0], SELB[1:0], QB0_OE
Pins QAC_OE, QA_OE, QB1_OE, IN_SEL,
BYPASS
V
CC
-
1.13
V
CC
-
1.18
V
CC
-
1.85
V
CC
-
1.90
0.6
200
48
40
0.72
350
50
50
V
CC
-
1.7
2
75
50
75
pF
k
k
k
LVPECL OUTPUT SPECIFICATIONS (QA,
QA,
QB0,
QB0,
QB1,
QB1
Pins)
T
A
= 0°C to +85°C
Output High Voltage
V
OH
T
A
= -40°C to 0°C
T
A
= 0°C to +85°C
Output Low Voltage
V
OL
T
A
= -40°C to 0°C
Peak-to-Peak Output-Voltage
Swing (Single-Ended)
Clock Output Rise/Fall Time
Output Duty-Cycle Distortion
(Note 2)
20% to 80% (Note 2)
PLL enabled
PLL bypassed (Note 5)
V
CC
-
0.98
V
CC
-
0.83
V
CC
-
0.83
V
CC
-
1.55
V
V
CC
-
1.55
0.9
600
52
60
V
P-P
ps
%
V
LVCMOS/LVTTL INPUT SPECIFICATIONS
(SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR,
BYPASS
Pins)
Input-Voltage High
Input-Voltage Low
V
IH
V
IL
2.0
0.8
V
V
2
_______________________________________________________________________________________
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
PARAMETER
Input High Current
Input Low Current
SYMBOL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
PLL enabled
PLL bypassed
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
PLL enabled
-240
30
2.5
V
OH
V
OL
QA_C sourcing 12mA
QA_C sinking 12mA
(Notes 3, 6)
PLL enabled
PLL bypassed (Note 5)
250
42
40
14
625
RJ
RMS
12kHz to 20MHz
1.875MHz to 20MHz
LVPECL output (Notes 7, 8, 9)
LVPECL output
LVCMOS output
0.36
0.14
5.0
-59
-47
-70
Between QB0 and QB1
Output Skew
Between QA and QB0 or QB1,
PECL outputs
f = 1kHz
f = 10kHz
Clock Output SSB Phase Noise
at 125MHz (Note 11)
f = 100kHz
f = 1MHz
f > 10MHz
15
20
-124
-125
-130
-145
-153
dBc/Hz
ps
1.0
MHz
ps
RMS
ps
P-P
dBc
dBc
500
50
2.6
0.4
1000
58
60
70
2.0
0.8
240
-80
25
320
CONDITIONS
MIN
TYP
MAX
80
UNITS
μA
μA
MAX3679A
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
Reference Clock Frequency
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
Reference Clock Duty Cycle
Input Capacitance
QA_C SPECIFICATIONS
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
Output Duty-Cycle Distortion
Output Impedance
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range
Random Jitter (Note 7)
Deterministic Jitter Due to
Supply Noise
Spurs Induced by Power-Supply
Noise (Notes 7, 9, 10)
Nonharmonic and Subharmonic
Spurs
V
V
ps
%
MHz
V
V
μA
μA
%
pF
Note 1:
A series resistor of up to 10.5Ω is allowed between V
CC
and V
CCA
for filtering supply noise when system power-supply
tolerance is V
CC
= 3.3V ±5%. See Figure 2.
_______________________________________________________________________________________
3
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
MAX3679A
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
Guaranteed up to 320MHz for LVPECL output.
Guaranteed up to 160MHz for LVCMOS output.
All outputs enabled and unloaded. IN_SEL set high.
Measured with crystal or AC-coupled, 50% duty-cycle signal on REF_IN.
Measured using setup shown in Figure 1 with V
CC
= 3.3V ±5%.
Measured with crystal source.
Total TIE including random and deterministic jitter. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope
using 2M sample record length.
Note 9:
Measured with 40mV
P-P
, 100kHz sinusoidal signal on the supply.
Note 10:
Measured at 156.25MHz output.
Note 11:
Measured with 25MHz crystal or 25MHz reference clock at LVCMOS input with a slew rate of 0.5V/ns or greater.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
MAX3679A
QA_C
36Ω
499Ω
4.7pF
0.1μF
Z
0
= 50Ω
OSCILLOSCOPE
50Ω
Figure 1. LVCMOS Output Measurement Setup
4
_______________________________________________________________________________________
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
Typical Operating Characteristics
(Typical values are at V
CC
= +3.3V, T
A
= +25°C, crystal frequency = 25MHz.)
MAX3679A
SUPPLY CURRENT
vs. TEMPERATURE
MAX3679A toc01
DIFFERENTIAL OUTPUT WAVEFORM
AT 156.25MHz (LVPECL OUTPUT)
MAX3679A toc02
OUTPUT WAVEFORM AT 125MHz
(LVCMOS OUTPUT)
MAX3679A toc03
250
225
200
SUPPLY CURRENT (mA)
175
150
125
100
75
50
25
0
-40
-15
10
35
60
ALL OUTPUTS ACTIVE AND UNTERMINATED
ALL OUTPUTS ACTIVE AND TERMINATED
MEASURED USING 50Ω OSCILLOSCOPE INPUT
THROUGH NETWORK SHOWN IN FIGURE 1
AMPLITUDE (200mV/div)
AMPLITUDE (50mV/div)
85
1ns/div
1ns/div
AMBIENT TEMPERATURE (°C)
PHASE NOISE AT 312.5MHz
CLOCK FREQUENCY
MAX3679A toc04
PHASE NOISE AT 125MHz
CLOCK FREQUENCY
-90
-100
-110
-120
-130
-140
-150
-160
MAX3679A toc05
-80
NOISE POWER DENSITY (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
0.1
1
10
100
-80
NOISE POWER DENSITY (dBc/Hz)
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
JITTER HISTOGRAM (312.5MHz OUTPUT,
40mV
P-P
SUPPLY NOISE AT 100kHz)
MAX3679A toc06
NOISE SPUR AMPLITUDE
vs. NOISE FREQUENCY
-10
SPUR AMPLITUDE (dBc)
-20
-30
-40
-50
-60
-70
-80
-90
10
100
1000
10,000
f
C
= 156.25MHz
NOISE AMPLITUDE = 40mV
P-P
MAX3679A toc07
0
DJ = 5.0ps
P-P
5ps/div
NOISE FREQUENCY (kHz)
_______________________________________________________________________________________
5
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