19-0547; Rev 3; 11/07
IT
TION K
VALUA
E
BLE
AVAILA
High-Precision Clock Generators
with Integrated VCXO
General Description
Features
♦
Integrated VCXO Provides a Cost-Effective
Solution for High-Precision Clocks
♦
8kHz to 500MHz Input Frequency Range
♦
15MHz to 160MHz Output Frequency Range
♦
I
2
C or SPI Programming for the Input and Output
Frequency Selection
♦
PLL Lock Range > ±60ppm
♦
Two Differential Outputs with Three Types of
Signaling: LVPECL, LVDS, or HSTL
♦
Input Clock Monitor with Hitless Switch
♦
Internal Holdover Function within ±20ppm of the
Nominal Frequency
♦
Low Output CLK Jitter: < 0.8ps RMS in the 12kHz
to 20MHz Band
♦
Low Phase Noise > -130dBc at 100kHz, > -140dBc
at 1MHz
MAX9450/MAX9451/MAX9452
The MAX9450/MAX9451/MAX9452 clock generators
provide high-precision clocks for timing in SONET/SDH
systems or Gigabit Ethernet systems. The MAX9450/
MAX9451/MAX9452 can also provide clocks for the high-
speed and high-resolution ADCs and DACs in 3G base
stations. Additionally, the devices can also be used as a
jitter attenuator for generating high-precision CLK signals.
The MAX9450/MAX9451/MAX9452 feature an integrated
VCXO. This configuration eliminates the use of an exter-
nal VCXO and provides a cost-effective solution for gen-
erating high-precision clocks. The MAX9450/MAX9451/
MAX9452 feature two differential inputs and clock out-
puts. The inputs accept LVPECL, LVDS, differential sig-
nals, and LVCMOS. The input reference clocks range
from 8kHz to 500MHz.
The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL,
and LVDS outputs, respectively. The output range is up
to 160MHz, depending on the selection of crystal. The
input and output frequency selection is implemented
through the I
2
C or SPI™ interface. The MAX9450/
MAX9451/MAX9452 feature clock output jitter less than
0.8ps RMS (in a 12kHz to 20MHz band) and phase-
noise attenuation greater than -130dBc/Hz at 100kHz.
The phase-locked loop (PLL) filter can be set externally,
and the filter bandwidth can vary from 1Hz to 20kHz.
The MAX9450/MAX9451/MAX9452 feature an input
clock monitor with a hitless switch. When a failure is
detected at the selected reference clock, the device
can switch to the other reference clock. The reaction to
the recovery of the failed reference clock can be
revertive or nonrevertive. If both reference clocks fail,
the PLL retains its nominal frequency within a range of
±20ppm at +25°C.
The MAX9450/MAX9451/MAX9452 operate from 2.4V to
3.6V supply and are available in 32-pin TQFP packages
with exposed pads.
Ordering Information
PART
MAX9450EHJ
MAX9451EHJ
MAX9452EHJ
PIN-PACKAGE
32 TQFP-EP*
32 TQFP-EP*
32 TQFP-EP*
OUTPUT
LVPECL
HSTL
LVDS
PKG CODE
H32E-6
H32E-6
H32E-6
Note:
All devices are specified over the -40°C to +85°C
temperature range.
For lead-free packages, contact factory.
*EP
= Exposed paddle.
Pin Configuration
CLK1+
CLK0+
CLK1-
V
DDQ
V
DDQ
18
GND
TOP VIEW
CLK0-
24
23
22
21
20
19
17
V
DD
25
X1 26
X2 27
V
DDA
28
LP1 29
LP2 30
GNDA 31
RJ 32
OE
16 CMON
15 AD1
14 AD0
13 SDA
12 SCL
11 GND/CS
10 MR
9
INT
8
IN1-
Applications
SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations
General Jitter Attenuation
MAX9450
MAX9451
MAX9452
EXPOSED PAD
(GND)
1
LOCK
2
SEL0
3
SEL1
4
IN0+
5
IN0-
6
V
DD
7
IN1+
SPI is a trademark of Motorola, Inc.
TQFP
(5mm x 5mm)
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Precision Clock Generators
with Integrated VCXO
MAX9450/MAX9451/MAX9452
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ...........................................................-0.3V to +4.0V
V
DDA
to GNDA ......................................................-0.3V to +4.0V
All Other Pins to GND ...................................-0.3V to V
DD
+ 0.3V
Short-Circuit Duration (all pins) ..................................Continuous
Continuous Power Dissipation (T
A
= +85°C)
32-Pin TQFP (derate 27.8mW/°C above +70°C)........2222mW
Storage Temperature Range .............................-65°C to +165°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model (R
D
= 1.5kΩ, C
S
= 100pF) ..............±2kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
DDA
= V
DD
= V
DDQ
= 2.4V to 3.6V, and V
DDQ
= 1.4V to 1.6V for MAX9451, T
A
= -40°C to +85°C. Typical values at V
DDA
= V
DD
=
V
DDQ
= 3.3V, and V
DDQ
= 1.5V for MAX9451, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Input High Level
Input Low Level
Input Current
LVCMOS OUTPUT (INT,
LOCK)
Output High Level
Output Low Level
THREE-LEVEL INPUT (AD0, AD1)
Input High Level
Input Low Level
Input Open Level
Input Current
DIFFERENTIAL INPUTS (IN0, IN1)
Differential Input High Threshold
Differential Input Low Threshold
Common-Mode Input-Voltage Range
Input Current
V
IDH
V
IDL
V
COM
I
IN+,
I
IN-
V
ID
= V
IN+
- V
IN-
V
ID
= V
IN+
- V
IN-
V
ID
= V
IN+
- V
IN-
-50
|V
ID
/ 2|
-1
V
DDQ
- 1.42
V
DDQ
- 2.15
V
DDQ
- 0.4V
2.4
- |V
ID
/ 2|
+1
V
DDQ
- 1.00
V
DDQ
- 1.70
50
mV
mV
V
µA
V
IH2
V
IL2
V
IO2
I
IL2,
I
IH2
Measured at the opened inputs
V
IL2
= 0V or V
IH2
= V
DD
1.05
-15
1.8
0.8
1.35
+15
V
V
V
µA
V
OH1
V
OL1
I
OH1
= -4mA
I
OL1
= 4mA
V
DD
- 0.4
0.4
V
V
SYMBOL
V
IH1
V
IL1
I
IN1
V
IN
= 0V to V
DD
CONDITIONS
MIN
2.0
0
-50
TYP
MAX
V
DD
0.8
+50
UNITS
V
V
µA
LVCMOS INPUT (SEL_,
CMON, OE,
MR)
MAX9450 OUTPUTS (CLK0, CLK1) (LVPECL)
Output High Voltage
Output Low Voltage
V
OH2
V
OL2
50Ω load connected to V
DDQ
- 2.0V
50Ω load connected to V
DDQ
- 2.0V
V
V
MAX9451 OUTPUTS (CLK0, CLK1) (differential HSTL)
Output High-Level Voltage
Output Low-Level Voltage
Differential Output Voltage
Change in V
OD
Between
Complementary Output States
V
OH3
V
OL3
V
OD
ΔV
OD
With 50Ω load resistor to GND, Figure 1
With 50Ω to GND and 16mA sink current
With a total 100Ω load, Figure 1
300
370
10
V
DDQ
0.4
450
35
V
V
mV
mV
MAX9452 OUTPUTS (CLK0, CLK1) (LVDS)
2
_______________________________________________________________________________________
High-Precision Clock Generators
with Integrated VCXO
DC ELECTRICAL CHARACTERISTICS (continued)
(V
DDA
= V
DD
= V
DDQ
= 2.4V to 3.6V, and V
DDQ
= 1.4V to 1.6V for MAX9451, T
A
= -40°C to +85°C. Typical values at V
DDA
= V
DD
=
V
DDQ
= 3.3V, and V
DDQ
= 1.5V for MAX9451, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Output Offset Voltage
Change in V
OS
Between
Complementary Output States
Output Short-Circuit Current
SYMBOL
V
OS
ΔV
OS
I
OS
Two output pins connected to GND
0.7
x V
DD
0.3
x V
DD
-1
3mA sink current
10
Output clock
frequency =
155MHz
Output clock
frequency =
155MHz (MAX9450)
MAX9450
MAX9451
MAX9452
MAX9450
MAX9451
MAX9452
55
70
65
55
65
14
85
94
88
80
80
25
+1
0.4
CONDITIONS
MIN
1.05
TYP
1.2
10
-7.5
MAX
1.35
35
-15
UNITS
V
mV
mA
MAX9450/MAX9451/MAX9452
SERIAL INTERFACE INPUT, OUTPUT (SCL, SDA,
CS)
Input High Level
Input Low Level
Input Leakage Current
Output Low Level
Input Capacitance
POWER CONSUMPTION
V
DD
and V
DDA
Supply Current
I
CC1
mA
V
IH
V
IL
I
IL
V
OL
C
I
V
V
µA
V
pF
V
DDQ
Supply Current
I
CC2
mA
AC ELECTRICAL CHARACTERISTICS
(V
DDA
= V
DD
= V
DDQ
= 2.4V to 3.6V, and V
DDQ
= 1.4V to 1.6V for MAX9451, T
A
= -40°C to +85°C. |V
ID
| = 200mV, V
COM
= |V
ID
/ 2| to
2.4 - |V
ID
/ 2|. Typical values at V
DDA
= V
DD
= V
DDQ
= 3.3V and V
DDQ
= 1.5V for MAX9451, T
A
= +25°C. C
L
= 10pF, clock output =
155.5MHz and clock input = 19.44MHz, unless otherwise noted.) (Note 1)
PARAMETER
CLK OUTPUTS (CLK0, CLK1)
Reference Input Frequency
Output Frequency
VCXO Pulling Range
Output-to-Output Skew
Rise Time
Fall Time
Duty Cycle
Period Jitter (RMS)
T
J
Measured at the band 12kHz to 20MHz
1kHz offset
Phase Noise
10kHz offset
100kHz offset
1MHz offset
t
SKO
t
R
t
F
f
IN
f
OUT
Measured at IN0 or IN1
Measured at CLK0 or CLK1
C
L
= 8pF (Note 2)
Skew between CLK0 and CLK1
(MAX9450 and MAX9452)
Skew between CLK0 and CLK1 (MAX9451)
20% to 80% of output swing
80% to 20% of output swing
43
0.8
-70
-110
-130
-140
dBc
50
55
0.4
0.4
0.008
15
500
160
±60
90
106
0.590
0.590
56
ns
ns
%
ps
MHz
MHz
ppm
ps
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_______________________________________________________________________________________
3
High-Precision Clock Generators
with Integrated VCXO
MAX9450/MAX9451/MAX9452
SERIAL I
2
C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS
(VDD = 2.4V to 3.6V, TA = -40°C to +85°C. See Figure 4 for the timing parameters definition.)
PARAMETER
Serial Clock
Bus Free Time Between STOP and
START Conditions
Repeated Hold Time START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock-Low Period
SCL Clock-High Period
Maximum Receive SCL/SDA Rise Time
Minimum Receive SCL/SDA Rise Time
Maximum Receive SCL/SDA Fall Time
Minimum Receive SCL/SDA Fall Time
Fall Time of SDA, Transmitting
Pulse Width of Suppressed Spike
Capacitive Load for Each Bus Line
SYMBOL
f
SCL
t
BUF
t
HD,STA
t
SU,STA
t
SU,STO
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
R
t
R
t
F
t
F
t
F,TX
t
SP
C
B
(Note 4)
(Note 4)
(Note 5)
(Note 4)
20
+ 0.1C
b
0
(Note 4)
(Note 3)
1.3
0.6
0.6
0.6
100
100
1.3
0.7
300
20
+ 0.1 x C
b
300
20
+ 0.1 x C
b
250
50
400
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
pF
SERIAL SPI INTERFACE TIMING CHARACTERISTICS
(VDD = 2.4V to 3.6V, TA = -40°C to +85°C. See Figure 7 for the timing parameters definition.)
PARAMETER
Serial-Clock Frequency
CS
Fall to CLK Rise Setup Time
DIN Setup Time
DIN Hold Time
CLK High to
CS
High
CS
Pulse-High Time
SYMBOL
f
SCL
t
CSS
t
DS
t
DH
t
CSH
t
CSW
12.5
12.5
0
0
20
CONDITIONS
MIN
TYP
MAX
2
UNITS
MHz
ns
ns
ns
ns
ns
Note 1:
All timing AC electrical characteristics and timing specifications are guaranteed by design and not production tested.
Note 2:
The VCXO tracks the input clock frequency by ±60ppm.
Note 3:
A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined regions of SCL’s
falling edge.
Note 4:
C
B
= total capacitance of one bus line in pF. Tested with C
B
= 400pF.
Note 5:
Input filters on SDA and SCL suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
High-Precision Clock Generators
with Integrated VCXO
Typical Operating Characteristics
(V
DD
= V
DDA
= V
DDQ
= 3.3V. T
A
= +25°C, unless otherwise noted.)
V
DD
AND V
DDA
SUPPLY CURRENT
vs. VOLTAGE (MAX9450)
MAX9450 toc01
MAX9450/MAX9451/MAX9452
V
DDQ
SUPPLY CURRENT
vs. VOLTAGE (MAX9450)
MAX9450 toc02
OUTPUT RMS JITTER
vs. TEMPERATURE
MAX9450 toc03
80
80
10
72
T
A
= +25°C
I
DD
+ I
DDA
(mA)
T
A
= -40°C
72
T
A
= -40°C
I
DDQ
(mA)
64
T
A
= +25°C
8
RMS JITTER (ps)
64
6
56
T
A
= +85°C
56
T
A
= +85°C
4
48
48
2
40
2.4
2.6
2.8
3.0
VOLTAGE (V)
3.2
3.4
3.6
40
2.4
2.6
2.8
3.0
VOLTAGE (V)
3.2
3.4
3.6
0
-40
-15
10
35
60
85
TEMPERATURE (°C)
OUTPUT FREQUENCY CHANGE
vs. TEMPERATURE
MAX9450 toc04
PHASE NOISE
vs. FREQUENCY
0
-20
-40
PHASE NOISE (dBc)
-60
-80
-100
-120
-140
MAX9450 toc05
OUTPUT CLOCK SYNCHRONIZED
TO INPUT REFERENCE
MAX9450 toc06
40
OUTPUT FREQUENCY CHANGE (ppm)
INPUT REFERENCE = 38.88 MHz
OUTPUT CLOCK = 155.52 MHz
153.13mV/div
100mV/div
INPUT REFERENCE = 19.44MHz
OUTPUT CLOCK = 155.52 MHz
20
0
-20
-40
-40
-15
10
35
60
85
TEMPERATURE (°C)
-160
1k
10k
100k
1M
FREQUENCY (Hz)
10M
10ns/div
_______________________________________________________________________________________
5
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