PRELIMINARY
DIFFERENTIAL-TO-0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
ICS871004I-04
G
ENERAL
D
ESCRIPTION
The ICS871004I-04 is a high perfor mance
Differential-to-0.7V Differential Jitter Attenuator
HiPerClockS™
designed for use in PCI Express™ systems. In some
PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, highphase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may
be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and
from the system board. The ICS871004I-04 has 3 PLL
bandwidth modes: 200kHz, 400kHz and 800kHz. The 200kHz
mode will provide maximum jitter attenuation, but with higher
PLL tracking skew and spread spectrum modulation from the
motherboard synthesizer may be attenuated. The 400kHz
provides an intermediate bandwidth that can easily track tri-
angular spread profiles, while providing good jitter attenuation.
The 800kHz bandwidth provides the best tracking skew and
will pass most spread profiles, but the jitter attenuation will not
be as good as the lower bandwidth modes. The ICS871004I-
04 can be set for different modes using the F_SEL pins as
shown in Table 3C.
Features
•
Four 0.7V differential output pairs
•
One differential clock input
•
CLK and nCLK supports the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 640MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 19ps (typical)
•
Additive phase jitter, RMS: 0.23ps (typical)
•
3.3V operating supply
•
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
IC
S
The ICS871004I-04 uses IDT’s 3
rd
Generation FemtoClock
TM
PLL
technology to achieve the lowest possible phase noise. The device
is packaged in a 24 Lead TSSOP package, making it ideal for
use in space constrained applications such as PCI Express add-
in cards.
PLL B
ANDWIDTH
BW_SEL[1:0]
0 0 = PLL Bandwidth: ~200kHz
0 1 = PLL Bandwidth: ~400kHz (default)
1 0 = PLL Bandwidth: ~800kHz
1 1 = PLL BYPASS
B
LOCK
D
IAGRAM
IREF
-
+
Pullup
P
IN
A
SSIGNMENT
nQ0
nQ2
Q2
V
DD
IREF
GND
MR
BW_SEL0
V
DDA
F_SEL0
V
DD
OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q0
V
DD
Q1
nQ1
Q3
nQ3
BW_SEL1
F_SEL1
GND
GND
nCLK
CLK
OE
F_SEL[1:0]
Pulldown
BW_SEL[1:0]
Pulldown:Pullup
2
2
Control
Logic
Q0
nQ0
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640MHz
M
U
X
0 0 ÷5
(default)
Q1
nQ1
0 1 ÷4
1 0 ÷2
1 1 ÷1
Q2
nQ2
ICS871004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
÷5
MR
Pulldown
Q3
nQ3
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
0.7V DIFFERENTIAL JITTER ATTUNUATOR
1
ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 24
2, 3
4, 11, 23
5
6, 15, 16
7
Name
nQ0, Q0
nQ2, Q2
V
DD
IREF
GND
MR
Type
Output
Output
Power
Input
Power
Input
Description
Differential output pair. PCI Express interface levels.
Differential output pair. PCI Express interface levels.
Core supply pin.
A fixed precision resistor (475
Ω
) from this pin to ground provides a
reference current used for differential current-mode QAx/nQAx and
QBx/nQBx clock outputs.
Power supply ground.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inver ted outputs
Pulldown
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pullup
See Table 3B.
Analog supply pin.
Frequency select pins. LVCMOS/LVTTL interface levels.
Pulldown
See Table 3C.
Output enable pin. When HIGH, the outputs are active. When LOW, the
Pullup
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pulldown
See Table 3B.
Differential output pair. PCI Express interface levels.
Differential output pair. PCI Express interface levels.
Pullup
8
9
1 0,
17
12
13
14
18
19, 20
21, 22
BW_SEL0
V
DDA
F_SEL0,
F_SEL1
OE
CLK
nCLK
BW_SEL1
nQ3, Q3
nQ1, Q1
Input
Power
Input
Input
Input
Input
Input
Output
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
0.7V DIFFERENTIAL JITTER ATTUNUATOR
2
ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OE
0
1
Q0:Q3
HiZ
Enabled
Outputs
nQ0:nQ3
HiZ
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
/PLL B
YPASS
C
ONTROL
Inputs
BW_SEL1
0
0
1
1
BW_SEL0
0
1
0
1
PLL Bandwidth
~200kHz
~400kHz (default)
~800kHz
PLL BYPASS
T
ABLE
3C. F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input Frequency
100
100
100
100
Inputs
F_SEL1
F_SEL0
0
0
0
1
1
1
0
1
Divider Value
5
4
2
1
Output Frequency Range
(MHz)
100 (default)
125
250
500
IDT
™
/ ICS
™
0.7V DIFFERENTIAL JITTER ATTUNUATOR
3
ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
82.3°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– I
DDA
*10
Ω
Typical
3.3
3.3
TBD
TBD
Maximum
3.465
V
DD
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
MR, OE,
F_SEL0. F_SEL1,
BW_SEL0, BW_SEL1
MR, OE,
F_SEL0. F_SEL1,
BW_SEL0, BW_SEL1
BW_SEL0, OE
MR, BW_SEL1,
F_SEL0. F_SEL1
BW_SEL0, OE
MR, BW_SEL1,
F_SEL0. F_SEL1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum Typical
2
V
DD
- 0.3
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
IL
I
IH
I
IL
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK,
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
1.3
V
DD
- 0.85
5
15 0
Minimum
Typical
Maximum
15 0
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK at V
DD
+ 0.3V.
IDT
™
/ ICS
™
0.7V DIFFERENTIAL JITTER ATTUNUATOR
4
ICS871004AGI-04 REV A JANUARY 17, 2008
ICS871004I-04
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
Refer to Additive Phase Jitter Section
Cycle-to-Cycle Jitter ; NOTE 2
PLL Lock Time
Voltage High
Voltage Low
Max. Voltage, Overshoot
Min. Voltage, Undershoot
Ringback Voltage
Absolute Crossing Voltage
Total Variation of V
CROSS
over all edges
Output Rise/Fall Time
Rise/Fall Time Variation
Rise/Fall Matching
Output Duty Cycle
50
measured between
0.175 to 0.525
475
125
125
250
-0.3
0.2
550
140
660
-150
V
HIGH
+ 0.3
PLL in BYPASS Mode
PLL in BYPASS Mode
100MHz, Integration Range:
12kHz - 20MHz
PLL Mode
Test Conditions
Minimum
98
3.8
0.23
19
TBD
850
Typical
Maximum
640
Units
MHz
ns
ps
ps
ms
mV
mV
V
V
V
mV
mV
ps
ps
ps
%
t
jit
t
jit(cc)
t
L
V
HIGH
V
LOW
V
OVS
V
UDS
V
rb
V
CROSS
ΔV
CROSS
t
R
/ t
F
Δt
R
/Δt
F
t
RFM
odc
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
0.7V DIFFERENTIAL JITTER ATTUNUATOR
5
ICS871004AGI-04 REV A JANUARY 17, 2008
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