PRELIMINARY
CRYSTAL-TO-LVDS PCI EXPRESS™
CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ICS844202-245
G
ENERAL
D
ESCRIPTION
The ICS844202-245 is a 2 output PCI Express™ clock
IC
S
synthesizer optimized to generate low jitter PCIe
HiPerClockS™
reference clocks with or without spread spectrum
modulation and is a member of the HiPerClockS™
family of high performance clock solutions from IDT.
Spread type and amount can be configured via the SSC control
pins. Using a 25MHz, 18pF parallel resonant crystal, the device
will generate LVDS clocks at either 25MHz, 100MHz, 125MHz or
250MHz. The ICS844202-245 uses a low jitter VCO that easily
meets PCI Express jitter requirements and is packaged in a
32-pin VFQFN package.
F
EATURES
• Two LVDS outputs at 25MHz, 100MHz, 125MHz or 250MHz
• Crystal oscillator interface, 25MHz, 18pF parallel resonant
crystal
• Supports the following output frequencies:
25MHz, 100MHz, 125MHz or 250MHz
• VCO range: 240MHz - 700MHz
• Supports SSC downspread at 0.50% and -0.75%,
centerspread at ±0.25% and no spread options
• Cycle-to-cycle jitter: 70ps (typical)
• Period jitter: 40ps (typical)
• Full 3.3V power supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
GND
GND
V
DDO
V
DDA
nQ1
nQ0
Q1
Q0
P
IN
A
SSIGNMENT
V
DD
V
DD
1
2
3
4
5
6
7
8
nc
nc
V
DDO
nc
FSEL0
OE
Pullup
Q0
25MHz
32 31 30 29 28 27 26 25
24
nc
nc
GND
nc
nc
SSC1
nc
GND
ICS844202-245
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
K Package
Top View
23
22
21
20
19
18
17
B
LOCK
D
IAGRAM
nc
9 10 11 12 13 14 15 16
FSEL1
SSC0
V
DD
OEB
XTAL_IN
XTAL_OUT
OE
GND
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
240-700MHz
00
01
10
11
PLL Bypass
÷5
÷4
÷2
nQ0
Q1
nQ1
Feedback Divider
÷20
SSC[1:0]
Pullup:Pullup
Default = 100MHz
Pulldown:Pullup
2
Spread Spectrum
Control
2
FSEL[1:0]
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
1
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Νυ μ β ε
Number
ρ
1, 2, 11
3, 4, 6, 8,
12, 18,
20, 21,
23, 2 4
5 , 27
7
9
10,
19
13, 14
15
16, 17,
22. 29.
30
25, 26
28
31, 32
Ναμ ε
Name
V
DD
nc
V
DDO
FSEL0
FSEL1
SSC0
SSC1
XTAL_IN,
XTAL_OUT
OE
GND
nQ1, Q1
V
DDA
nQ0, Q0
Power
Unused
Power
Input
Input
Input
Input
Input
Power
Output
Power
Output
Pullup
Τψπ ε
Type
Δ ε σχριπ τιο ½
Description
Core supply pins.
No connect.
Output supply pins.
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Pulldown Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Spread spectrum control pins. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
Pullup
XTAL_IN is the input. (PLL reference.)
Output enable pin. Logic HIgh, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Analog supply pin.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pulllup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. FSEL[1:0] F
UNCTION
T
ABLE
Input
FSEL1
0
0
1
1
FSEL0
0
1
0
1
Outputs
Q0:1/nQ0:1
PLL Bypass (25MHz)
100MHz (default)
125MHz
250MHz
T
ABLE
3B. SSC[1:0] F
UNCTION
T
ABLE
Input
SSC1
0
0
1
1
SSC0
0
1
0
1
Spread %
Center ± -0.25
Down -0.5
Down -0.75
No Spread (default)
IDT
™
/ ICS
™
LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
2
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
42.4°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.12
3.135
Typical
3. 3
3. 3
3.3
83
12
26
Maximum
3.465
V
DD
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
FSEL1
SSC0, SSC1,
FSEL0, OE
FSEL1
SSC0, SSC1,
FSEL0, OE
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0. 8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
50
1.33
50
Maximum
Units
mV
mV
V
mV
IDT
™
/ ICS
™
LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
3
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
TBD
7
100
Maximum
Units
MHz
Ω
pF
µW
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
Typical
25
f
OUT
Output Frequency
125
100
250
25MHz
t
jit(per)
Period Jitter, RMS
100MHz
125MHz
250MHz
25MHz
100MHz
125MHz
250MHz
t
sk(o)
F
xtal
F
M
F
MF
SSC
red
t
STABLE
t
R
/ t
F
odc
Output Skew; NOTE 2, 3
Crystal Input Range; NOTE 1
SSC Modulation Frequency; NOTE 4
SSC Modulation Factor; NOTE 4
Spectral Reduction; NOTE 5
Power-up to Stable Clock Output
Output Rise/Fall Time
Output Duty Cycle
20% - 80%
525
50
12
35
45
40
40
60
70
60
70
40
25
TBD
TBD
11
10
35
Maximum
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
MHz
kHz
%
dB
ms
ps
%
t
j it(cc)
Cycle-to-Cycle Jitter; NOTE 1, 2
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Only valid within the VCO operating range.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Spread Spectrum clocking enabled.
IDT
™
/ ICS
™
LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
4
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
OH
V
REF
V
OL
SCOPE
3.3V±10%
POWER SUPPLY
+ Float GND –
V
DD
,
V
DDO
Qx
V
DDA
LVDS
nQx
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ERIOD
J
ITTER
nQx
Qx
nQy
Qy
tsk(o)
nQ0, nQ1
Q0, Q1
tcycle
n
➤
tjit(cc)
=
tcycle
n –
tcycle
n+1
1000 Cycles
O
UTPUT
S
KEW
C
YCLE
-
TO
-C
YCLE
J
ITTER
nQ0, nQ1
80%
Clock
Outputs
80%
V
OD
20%
t
R
t
F
odc =
Q0, Q1
t
PW
t
PERIOD
20%
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
IDT
™
/ ICS
™
LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
5
ICS844202BK-245 REV. A JULY 9, 2007
➤
➤
tcycle
n+1
➤
x 100%
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