LTC3413
3A, 2MHz Monolithic
Synchronous Regulator for
DDR/QDR Memory Termination
FEATURES
s
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DESCRIPTIO
High Efficiency: Up to 90%
±3A
Output Current
Symmetrical Source and Sink Output Current Limit
Low R
DS(ON)
Internal Switch: 85mΩ
No Schottky Diode Required
2.25V to 5.5V Input Voltage Range
V
OUT
= V
REF
/2
±1%
Output Voltage Accuracy
Programmable Switching Frequency: Up to 2MHz
Power Good Output Voltage Monitor
Overtemperature Protected
Available in 16-Lead TSSOP Exposed Pad Package
The LTC
®
3413 is a high efficiency monolithic synchro-
nous step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage equal to (0.5)V
REF
while sourcing
or sinking up to 3A of output current. An internal voltage
divider reduces component count and eliminates the need
for external resistors by dividing the reference voltage in
half. The internal synchronous power switch with 85mΩ
on-resistance increases efficiency and eliminates the need
for an external Schottky diode. Switching frequencies up
to 2MHz are set by an external resistor.
Forced-continuous operation in the LTC3413 reduces
noise and RF interference. Fault protection is provided by
an overcurrent comparator that limits output current dur-
ing both sourcing and sinking operations. Adjustable
compensation allows the transient response to be opti-
mized over a wide range of loads and output capacitors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
APPLICATIO S
s
s
s
Bus Termination: DDR and QDR
TM
Memory,
SSTL, HSTL, ...
Notebook Computers
Distributed Power Systems
TYPICAL APPLICATIO
V
IN
2.5V
100
22µF
SV
IN
V
REF
4.7M
330pF
LTC3413
RUN/SS
5.11k
I
TH
2200pF
R
T
309k
V
FB
3413 F01a
90
80
V
IN
= 2.5V
f = 1MHz
PV
IN
PGOOD
SW
PGND
SGND
C
OUT
100µF
×2
V
OUT
1.25V
±3A
EFFICIENCY (%)
L1
0.47µH
70
60
50
40
30
20
10
0
0.01
0.1
1
LOAD CURRENT (A)
10
3413 F01b
L1: VISHAY DALE IHLP-2525CZ-01 0.47
C
OUT
: TDK C4532X5R0J107M
Figure 1a. High Efficiency Bus Termination Supply
Figure 1b. Efficiency vs Load Current
sn3413 3413fs
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1
LTC3413
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SV
IN
PGOOD
I
TH
V
FB
R
T
V
REF
RUN/SS
SGND
1
2
3
4
5
6
7
8
17
16 PV
IN
15 SW
14 SW
13 PGND
12 PGND
11 SW
10 SW
9
PV
IN
SV
IN
, PV
IN
Supply Voltages ........................ – 0.3V to 6V
I
TH
, RUN/SS, V
FB
, PGOOD Voltages ........... – 0.3V to V
IN
V
REF
Voltage .............................................. – 0.3V to V
IN
SW Voltage .................................. – 0.3V to (V
IN
+ 0.3V)
Peak SW Sink and Source Current ........................ 7.2A
Operating Ambient Temperature Range
(Note 2) .............................................. – 40°C to 85°C
Junction Temperature (Notes 5, 8) ...................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LTC3413EFE
FE PART
MARKING
3413EFE
FE PACKAGE
16-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17)
MUST BE SOLDERED TO SGND
T
JMAX
= 125°C,
θ
JA
= 38°C/ W,
θ
JC
= 10°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL
V
IN
V
FB
I
FB
I
RUN
∆V
FB
V
LOADREG
∆V
PGOOD
R
PGOOD
I
Q
PARAMETER
Input Voltage Range
Feedback Voltage Accuracy
Voltage Feedback Leakage Current
RUN/SS Leakage Current
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Power Good Range
Power Good Pull-Down Resistance
Input DC Bias Current
Active Current
Shutdown
Switching Frequency
Switching Frequency Range
R
DS(ON)
of P-Channel FET
R
DS(ON)
of N-Channel FET
Peak Current Limit
Undervoltage Lockout Threshold
SW Leakage Current
RUN Threshold
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 3.3V, unless otherwise noted.
CONDITIONS
(Note 3)
q
MIN
2.25
TYP
MAX
5.5
±1
0.4
1
UNITS
V
%
µA
µA
%/V
%
%
%
Ω
µA
µA
MHz
MHz
mΩ
mΩ
A
V
µA
V
V
IN
= 2.7V to 5.5V (Note 3)
Measured in Servo Loop, V
ITH
= 0.36V
Measured in Servo Loop, V
ITH
= 0.84V
q
q
q
0.04
0.02
– 0.02
±10
120
0.2
0.2
– 0.2
±12
200
330
1
1.12
2.00
110
90
2.25
1
0.8
(Note 4)
V
FB
= 1.5V, V
ITH
= 1.4V, V
REF
= 2.5V
V
RUN
= 0V (Note 7)
R
OSC
= 309k
(Note 6)
I
SW
= 300mA
I
SW
= 300mA
3.8
1.75
V
RUN
= 0V, V
IN
= 5.5V (Note 7)
0.5
0.88
0.30
250
0.02
1.00
85
65
5.4
2
0.1
0.65
f
OSC
R
PFET
R
NFET
I
LIMIT
V
UVLO
I
LSW
V
RUN
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
The LTC3413E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3:
The LTC3413E is tested in a feedback loop that adjusts V
FB
to
achieve a specified error amplifier output voltage (I
TH
).
Note 4:
Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5:
T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
as follows: LTC3413E: T
J
= T
A
+ (P
D
• 38°C/W)
Note 6:
2MHz operation is guaranteed by design and not production tested.
Note 7:
Shutdown current and SW leakage current are only tested during
wafer sort.
Note 8:
This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
sn3413 3413fs
2
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LTC3413
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
100
V
OUT
= 1.25V
90 T
A
= 25°C
80
EFFICIENCY (%)
100
EFFICIENCY (%)
60
50
40
30
20
10
0
0.01
V
IN
= 3.3V
70
LOAD = 100mA
60
50
40
30
∆V
OUT
/V
OUT
(%)
70
V
IN
= 2.5V
0.1
1
LOAD CURRENT (A)
Switch On-Resistance
vs Temperature
120
100
V
IN
= 3.3V
PFET
ON-RESISTANCE
80
60
40
20
0
–40 –20
NFET
ON-RESISTANCE
80
60
NFET ON-RESISTANCE
40
20
0
LEAKAGE CURRENT (nA)
ON-RESISTANCE (mΩ)
ON-RESISTANCE (mΩ)
0
20 40 60 80
TEMPERATURE (°C)
Frequency vs R
OSC
4500
4000
3500
V
IN
= 3.3V
T
A
= 25°C
FREQUENCY (kHz)
FREQUENCY (kHz)
3000
2500
2000
1500
1000
1030
1020
1010
1000
FREQUENCY (kHz)
500
0
54 154 254 354 454 554 654 754 854 954
R
OSC
(kΩ)
3413 G07
U W
3413 G01
3413 G04
Efficiency vs Input Voltage
V
OUT
= 1.25V
T
A
= 25°C
90
80
Load Regulation
0
T
A
= 25°C
LOAD = 1A
–0.05
LOAD = 3A
–0.10
–0.15
–0.20
–0.25
–0.30
10
20
2.5
3.0
4.5
4.0
INPUT VOLTAGE (V)
3.5
5.0
5.5
3413 G02
0
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
2.5
3.0
3413 G03
Switch On-Resistance
vs Input Voltage
120
100
PFET ON-RESISTANCE
T
A
= 25°C
2.5
Switch Leakage vs Input Voltage
T
A
= 25°C
2.0
1.5
PFET
1.0
NFET
0.5
0
100 120
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
3413 G05
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
5.5
3413 G06
Frequency vs Input Voltage
1050
1040
T
A
= 25°C
1010
1008
1006
1004
1002
1000
998
996
994
992
Frequency vs Temperature
V
IN
= 3.3V
990
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
5.5
3213 G08
990
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
3413 G09
sn3413 3413fs
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LTC3413
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs Input Voltage
350
300
T
A
= 25°C
QUIESCENT CURRENT (µA)
250
200
150
100
50
0
2.0
2.5
Load Step Transient
OUTPUT
VOLTAGE
100mV/DIV
OUTPUT
VOLTAGE
500mV/DIV
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
1A/DIV
20µs/DIV
V
IN
= 2.5V
V
OUT
= 1.25V
LOAD STEP = 0A TO –3A
4
U W
Load Step Transient
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
1A/DIV
V
IN
= 2.5V
20µs/DIV
V
OUT
= 1.25V
LOAD STEP = 0A TO 3A
4.5
3.0 3.5 4.0
INPUT VOLTAGE (V)
5.0
5.5
3413 G11
3413 G10
Start-Up
3413 G12
V
IN
= 2.5V
V
OUT
= 1.25V
LOAD = 0.4Ω
1ms/DIV
3413 G13
sn3413 3413fs
LTC3413
PI FU CTIO S
SV
IN
(Pin 1):
Signal Input Supply. Decouple this pin to
SGND with a capacitor. SV
IN
must be greater or equal to
PV
IN
, however, the difference between SV
IN
and PV
IN
must
be less than 0.5V.
PGOOD (Pin 2):
Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within
±10%
of regulation point.
I
TH
(Pin 3):
Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.6V corresponding to the zero-sense voltage
(zero current).
V
FB
(Pin 4):
Feedback Pin. Receives the feedback voltage
from the output.
R
T
(Pin 5):
Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
V
REF
(Pin 6):
Reference Voltage Input. The positive input
of the internal error amplifier senses one-half of the
voltage at this pin through a resistor divider.
RUN/SS (Pin 7):
Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3413. In shutdown
all functions are disabled drawing < 1µA of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 8):
Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
PV
IN
(Pins 9, 16):
Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 10, 11, 14, 15):
Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
PGND (Pins 12, 13):
Power Ground. Connect this pin
closely to the (–) terminal of C
IN
and C
OUT
.
EXPOSED PAD (Pin 17):
Should be connected to SGND.
FU CTIO AL DIAGRA
SV
IN
1
V
REF
6
SV
IN
SGND
8
V
FB
4
SLOPE
COMPENSATION
RECOVERY
PGOOD
2
–
1.1V
REF
2
+
0.9V
REF
2
W
+
+
–
–
U
U
U
U
U
I
TH
3
PV
IN
PV
IN
9
16
PMOS CURRENT
COMPARATOR
+
–
SLOPE
COMPENSATION
ERROR
AMPLIFIER
OSCILLATOR
10 SW
11 SW
LOGIC
–
+
14 SW
15 SW
RUN
NMOS CURRENT
COMPARATOR
12 PGND
13 PGND
3413 BD
5
R
T
7
RUN/SS
sn3413 3413fs
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