54F 74F402 Serial Data Polynomial Generator Checker
January 1995
54F 74F402 Serial Data Polynomial
Generator Checker
General Description
The ’F402 expandable Serial Data Polynomial generator
checker is an expandable version of the ’F401 It provides
an advanced tool for the implementation of the most widely
used error detection scheme in serial digital handling sys-
tems A 4-bit control input selects one-of-six generator poly-
nomials The list of polynomials includes CRC-16 CRC-
CCITT and Ethernet as well as three other standard poly-
nomials (56
th
order 48
th
order 32
nd
order) Individual clear
and preset inputs are provided for floppy disk and other
applications The Error output indicates whether or not a
transmission error has occurred The CWG Control input
inhibits feedback during check word transmission The
’F402 is compatible with FAST devices and with all TTL
families
Features
Y
Y
Y
Y
Y
Y
Y
Y
Guaranteed 30 MHz data rate
Six selectable polynomials
Other polynomials available
Separate preset and clear controls
Expandable
Automatic right justification
Error output open collector
Typical applications
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
Commercial
74F402PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F402DM (Note 1)
54F402FM (Note 1)
54F402LM (Note 1)
J16A
W16A
E20A
Note 1
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9535 – 1
TL F 9535 – 2
TL F 9535–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
Ethernet is a registered trademark of Xerox Corporation
C
1995 National Semiconductor Corporation
TL F 9535
RRD-B30M105 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
1 0 0 67
1 0 0 67
285(100) 13 3(6 7)
1 0 0 67
26 7(13 3)
285(100) 13 3(6 7)
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 4 mA
20
mA
b
0 4 mA
b
5 7 mA(
b
2 mA) 8 mA (4 mA)
20
mA
b
0 4 mA
16 mA (8 mA)
b
5 7 mA(
b
2 mA) 8 mA (4 mA)
20
mA
b
0 4 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
S
0
–S
3
CWG
D CW
D
ER
RO
CP
SEI
RFB
MR
P
Open Collector
Polynomial Select Inputs
Check Word Generate Input
Serial Data Check Word
Data Input
Error Output
Register Output
Clock Pulse
Serial Expansion Input
Register Feedback
Master Reset
Preset
Functional Description
The ’F402 Serial Data Polynomial Generator Checker is an
expandable 16-bit programmable device which operates on
serial data streams and provides a means of detecting
transmission errors Cyclic encoding and decoding schemes
for error detection are based on polynomial manipulation in
modulo arithmetic For encoding the data stream (message
polynomial) is divided by a selected polynomial This divi-
sion results in a remainder (or residue) which is appended to
the message as check bits For error checking the bit
stream containing both data and check bits is divided by the
same selected polynomial If there are no detectable errors
this division results in a zero remainder Although it is possi-
ble to choose many generating polynomials of a given de-
gree standards exist that specify a small number of useful
polynomials The ’F402 implements the polynomials listed in
Table I by applying the appropriate logic levels to the select
pins S
0
S
1
S
2
and S
3
The ’F402 consists of a 16-bit register a Read Only Memory
(ROM) and associated control circuitry as shown in the
Block Diagram The polynomial control code presented at
inputs S
0
S
1
S
2
and S
3
is decoded by the ROM selecting
the desired polynomial or part of a polynomial by establish-
ing shift mode operation on the register with Exclusive OR
(XOR) gates at appropriate inputs To generate the check
bits the data stream is entered via the Data Inputs (D) us-
ing the LOW-to-HIGH transition of the Clock Input (CP) This
data is gated with the most significant Register Output (RO)
via the Register Feedback Input (RFB) and controls the
XOR gates The Check Word Generate (CWG) must be held
HIGH while the data is being entered After the last data bit
is entered the CWG is brought LOW and the check bits are
shifted out of the register(s) and appended to the data bits
(no external gating is needed)
To check an incoming message for errors both the data
and check bits are entered through the D Input with the
CWG Input held HIGH The Error Output becomes valid af-
ter the last check bit has been entered into the ’F402 by a
LOW-to-HIGH transition of CP with the exception of the
Ethernet polynomial (see Applications paragraph) If no de-
tectable errors have occurred during the data transmission
the resultant internal register bits are all LOW and the Error
Output (ER) is HIGH If a detectable error has occurred ER
is LOW ER remains valid until the next LOW-to-HIGH tran-
sition of CP or until the device has been preset or reset
A HIGH on the Master Reset Input (MR) asynchronously
clears the entire register A LOW on the Preset Input (P)
asynchronously sets the entire register with the exception
of
1 The Ethernet residue selection in which the registers
containing the non-zero residue are cleared
2 The 56th order polynomial in which the 8 least significant
register bits of the least significant device are cleared
and
3 Register S
e
0 in which all bits are cleared
2
TABLE I
Hex
0
C
D
E
F
7
B
3
2
4
8
5
9
1
6
A
S
3
L
H
H
H
H
L
H
L
L
L
H
L
H
L
L
H
Select Code
S
2
S
1
L
H
H
H
H
H
L
L
L
H
L
H
L
L
H
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
H
H
S
0
L
L
H
L
H
H
H
H
L
L
L
H
H
H
L
L
0
X
32
a
X
26
a
X
23
a
X
22
a
X
16
a
X
12
a
X
11
a
X
10
a
X
8
a
X
7
a
X
5
a
X
4
a
X
2
a
X
a
1
X
32
a
X
31
a
X
27
a
X
26
a
X
25
a
X
19
a
X
16
a
X
15
a
X
13
a
X
12
a
X
11
a
X
9
a
X
7
a
X
6
a
X
5
a
X
4
a
X
2
a
X
a
1
X
16
a
X
15
a
X
2
a
1
X
16
a
X
12
a
X
5
a
1
X
56
a
X
55
a
X
49
a
X
45
a
X
41
a
X
39
a
X
38
a
X
37
a
X
36
a
X
31
a
X
22
a
X
19
a
X
17
a
X
16
a
X
15
a
X
14
a
X
12
a
X
11
a
X
9
a
X
5
a
X
a
1
X
48
a
X
36
a
X
35
a
X
23
a
X
21
a
X
15
a
X
13
a
X
8
a
X
2
a
1
X
32
a
X
23
a
X
21
a
X
11
a
X
2
a
1
Polynomial
Remarks
S
e
0
Ethernet
Polynomial
Ethernet
Residue
CRC-16
CRC-CCITT
56th
Order
48th
Order
32nd
Order
Block Diagram
TL F 9535 – 5
3
TABLE II
Select Code
0
C
D
E
F
7
B
3
2
4
8
5
9
1
6
A
P
3
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
P
2
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
P
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
P
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
C
2
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
C
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
C
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Polynomial
S
e
0
Ethernet
Polynomial
Ethernet
Residue
CRC-16
CRC-CCITT
56th
Order
48th
Order
32nd
Order
Applications
In addition to polynomial selection there are four other ca-
pabilities provided for in the ’F402 ROM The first is set or
clear selectability The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW This set or clear capability is done in four groups of 4
(see Table II P
0
–P
3
) The second ROM capability (C
0
) is in
determining the polarity of the check word As is the case
with the Ethernet polynomial the check word can be invert-
ed when it is appended to the data stream or as is the case
with the other polynomials the residue is appended with no
inversion Thirdly the ROM contains a bit (C
1
) which is used
to select the RFB input instead of the SEI input to be fed
into the LSB This is used when the polynomial selected is
actually a residue (least significant) stored in the ROM
which indicates whether the selected location is a polynomi-
al or a residue If the latter then it inhibits the RFB input
As mentioned previously upon a successful data transmis-
sion the CRC register has a zero residue There is an ex-
ception to this however with respect to the Ethernet poly-
nomial This polynomial upon a successful data transmis-
sion has a non-zero residue in the CRC register (C7 04 DD
7B)
16
In order to provide a no-error indication two ROM
locations have been preloaded with the residue so that by
selecting these locations and clocking the device one addi-
tional time after the last check bit has been entered will
result in zeroing the CRC register In this manner a no-error
indication is achieved
With the present mix of polynomials the largest is 56
th
or-
der requiring four devices while the smallest is 16
th
order
requiring just one device In order to accommodate multi-
plexing between high order polynomials (X 16
th
order) and
lower order polynomials a location of all zeros is provided
This allows the user to choose a lower order polynomial
even if the system is configured for a higher order one
The ’F402 expandable CRC generator checker contains 6
popular CRC polynomials 2-16
th
Order 2-32
nd
Order 1-
48
th
Order and 1-56
th
Order The application diagram
shows the ’F402 connected for a 56
th
Order polynomial
Also shown are the input patterns for other polynomials
When the ’F402 is used with a gated clock disabling the
clock in a HIGH state will ensure no erroneous clocking
occurs when the clock is re-enabled Preset and Master Re-
set are asynchronous inputs presetting the register to S or
clearing to 1s respectively (note Ethernet residue and 56
th
Order select code 8 LSB are exceptions to this)
To generate a CRC the pattern for the selected polynomial
is applied to the S inputs the register is preset or cleared as
required clock is enabled CWG is set HIGH data is applied
to D input output data is on D CW When the last data bit
has been entered CWG is set LOW and the register is
clocked for n bits (where n is the order of the polynomial)
The clock may now be stopped if desired (holding CWG
LOW and clocking the register will output zeros from D CW
after the residue has been shifted out)
To check a CRC the pattern for the selected polynomial is
applied to the S inputs the register is preset or cleared as
required clock is enabled CWG is set HIGH the data
stream including the CRC is applied to D input When the
last bit of the CRC has been entered the ER output is
checked HIGH
e
error free data LOW
e
corrupt data The
clock may now be stopped if desired
To implement polynomials of lower order than 56
th
select
the number of packages required for the order of polynomial
and apply the pattern for the selected polynomial to the S
inputs (0000 on S inputs disables the package from the
feedback chain)
4
Applications
(Continued)
TL F 9535 – 6
5
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