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CD40108BFMSR

产品描述4X4 MULTI-PORT SRAM, 972ns, CDIP24, FRIT SEALED, DIP-24
产品类别存储    存储   
文件大小157KB,共11页
制造商Intersil ( Renesas )
官网地址http://www.intersil.com/cda/home/
下载文档 详细参数 全文预览

CD40108BFMSR概述

4X4 MULTI-PORT SRAM, 972ns, CDIP24, FRIT SEALED, DIP-24

CD40108BFMSR规格参数

参数名称属性值
Objectid1529386560
零件包装代码DIP
包装说明DIP,
针数24
Reach Compliance Codeunknown
ECCN代码3A001.A.2.C
最长访问时间972 ns
JESD-30 代码R-GDIP-T24
JESD-609代码e0
内存密度16 bit
内存集成电路类型MULTI-PORT SRAM
内存宽度4
功能数量1
端子数量24
字数4 words
字数代码4
工作模式SYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织4X4
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class V
座面最大高度5.72 mm
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层TIN LEAD
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
总剂量100k Rad(Si) V
宽度15.24 mm

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CD40108BMS
December 1992
CMOS 4 x 4 Multiport Register
Description
The CD40108BMS is a 4 x 4 multiport register containing
four 4-bit registers, write address decoder, two separate
read address decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output
bus is switched, independently of the clock, to a high-imped-
ance state. The high-impedance third state provides the out-
puts with the capability of being connected to the bus lines in
a bus-organized system without the need for interface or
pull-up components.
When the WRITE ENABLE input is high, all data input lines
are latched on the positive transition of the CLOCK and the
data is entered into the word selected by the write address
lines. When WRITE ENABLE is low, the CLOCK is inhibited
and no new data is entered. In either case, the contents of
any word may be accessed via the read address lines inde-
pendent of the state of the CLOCK input.
The CD40108BMS is supplied in these 24-lead outline pack-
ages:
Braze Seal DIP
Ceramic Flatpack
H4V
H4P
Features
• High Voltage Type (20V Rating)
• Four 4-Bit Registers
• One Input and Two Output Buses
• Unlimited Expansion in Bit and Word Directions
• Data Lines have latched Inputs
• 3-State Outputs
• Separate Control of Each Bus, Allowing Simultaneous
Independent Reading of Any of Four Registers on Bus
A and Bus B and Independent Writing Into Any of the
Four Registers
• CD40108BMS is Pin-Compatible with Industry Type
MC14580
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Scratch-Pad Memories
• Arithmetic Units
• Data Storage
Pinout
CD40108BMS
TOP VIEW
Q3 B 1
Q2 B 2
3-STATE A 3
Q0 A 4
Q1 A 5
Q2 A 6
Q3 A 7
WRITE 0 8
WRITE 1 9
READ 1B 10
READ 0B 11
VSS 12
24 VDD
23 Q1 B
22 Q0 B
21 3-STATE B
20 D0
19 D1
18 D2
17 D3
16 CLOCK
15 WRITE ENABLE
14 READ 1A
13 READ 0A
Functional Diagram
WRITE
ENABLE
D0
DATA
INPUTS
D1
D2
D3
WRITE 0
WRITE 1
READ 1A
READ 0A
READ 1B
READ 0B
VDD = 24
VSS = 12
20
19
18
17
8
9
14
13
10
11
16
CLOCK
21
3-STATE B
22
23
2
1
Q0
Q1
Q2
Q3
WORD B
OUTPUT
3-STATE A
15
3
4
5
6
7
Q0
Q1
Q2
Q3
WORD A
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3356
7-25

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