CALIFORNIA MICRO DEVICES
CM88L70/70C
CMOS INTEGRATED DTMF RECEIVER, 3 VOLT VERSION
Features
2.7 to 3.6 volt operating range
Full DTMF receiver
Less than 18mW power consumption
Industrial temperature range
Uses quartz crystal or ceramic resonators
Adjustable acquisition and release times
18-pin DIP, 20-pin QSOP, 18-pin SOIC,
20-pin PLCC, 20-pin TSSOP
CM88L70
- Power down mode
- Inhibit mode
- Buffered oscillator output (OSC 3) to
drive other devices
Applications
PCMCIA
Portable TAD
Mobile radio
Remote control
Remote data entry
Call limiting
Telephone answering systems
Paging systems
Product Description
The CAMD CM88L70/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital decoder
functions into a single 18-pin DIP, SOIC, or 20-pin PLCC, TSSOP, or QSOP package. The CM88L70/70C is manufactured using
state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The filter
section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The CM88L70/70C
decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This
DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and
a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as
an external component.
Block Diagram
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
C0451098
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
Absolute Maximum Ratings: (Note 1)
CM88L70/70C
This device contains input protection against
damage due to high static voltages or
electric fields; however, precautions should
be taken to avoid application of voltages
higher than the maximum rating.
Note:
1. Exceeding these ratings may cause
permanent damage, functional
operation under these conditions is not
implied.
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage (V
DD
-
V
SS
)
Voltage on any Pin
Current on any Pin
Storage Temperature
Symbol
V
DD
V
t
I
t
T
S
Value
6.0V Max
V
SS
-0.3V to V
DD
+0.3V
10mA Max
-65°C to +150°C
DC Characteristics:
All voltages referenced to V
SS
, V
DD
= 3.0V + 20% / -10%, T
A
= -40°C to +85°C unless otherwise noted.
Parameter
Operating Supply Voltage
Operating Supply Current
Standby Supply Current
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Pull Up (Source) Current on TOE
Pull down (sink) Current PD
Pull down (sink) Current INH
Input Impedance, (IN+, IN-)
Steering Threshold Voltage
Low Level Output Voltage
High Level Output Voltage
Output High (Source) Current
Output Voltage
Output Resistance
Symbol
V
DD
I
DD
I
DDS
V
IL
V
IH
I
I H
/ L
I L
I
so
I
PD
I
I NH
R
IN
V
Tst
V
OL
V
OH
I
OH
V
R EF
R
OR
DC CHARACTE RISTICS
Min
Typ
Max
Units
2.7
3.0
3.0
5.0
2.0
0.1
-12
-2.0
1.0
1.0
10
1.5
0.1
2.4
1.0
1.5
10
2.6
0.4
45
45
3.6
5.0
10
1.0
V
mA
µA
V
V
µA
µA
µA
µA
MΩ
V
V
V
mA
V
ΚΩ
Test Conditions
V
PD =V
DD
V
DD
=3.0V
V
DD
=3.0V
V
IN
= V
SS
or V
DD
(Note 11)
TOE = 0V
PD = 3.0V
IHN = 3.0V
@ 1K H z
I
OL
= 1.0mA
I
OH
= 400
µA
V
OUT
= 2.5V @ V
DD
= 2.7V
N o L o ad
V
REF
Operating Characteristics:
All voltages referenced to V
SS
, V
DD
= 3.0V + 20% / -10%, T
A
= -40°C to +85°C unless otherwise noted.
Gain Setting Amplifier
OPERATING CHARACTERISTICS
Parameter
Input Leakage Current
Input Resistance
Input Offset Voltage
Power Supply Rejection
Common Mode Rejection
D C Open Loop Voltage Gain
Open Loop Unity Gain Bandwidth
Output Voltage Swing
Tolerable Capacitive Load (GS)
Tolerable Resistive Load (GS)
Common Mode Range (No Load)
©2000 California Micro Devices Corp. All rights reserved.
Symbol
I
IN
R
IN
V
OS
PSRR
CMR R
A
VOL
fc
V
O
C
L
R
L
Vcm
Min
Typ
10 0
10
15
Max
Units
nA
MΩ
Test Conditions
V
SS
< V
IN
< V
DD
25
mV
dB
dB
dB
MH z
V
P-P
R
L
≥
100K
Ω
to V
SS
1KHz (Note 12)
-3.0V < V
IN
< 3.0V
50
40
32
0.3
60
60
65
1.0
2.2
10 0
pF
K
Ω
V
P-P
N o L o ad
5.0
1.5
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8/16/2000
CALIFORNIA MICRO DEVICES
CM88L70/70C
AC Characteristics:
All voltages referenced to V
SS
, V
DD
=3.0V + 20% / -10%, T
A
=-40°C to +85°C, f
CLK
=3.579545 MHz
using test circuit (Fig. 1) unless otherwise noted.
AC CHARACTERISTICS
Parameter
Valid Input Signal Levels
(each tone of composite signal)
Positive Twist Accept
Negative Twist Accept
Freq. D eviation Accept Limit
Freq. D eviation Reject Limit
Third Tone Tolerance
Noise Tolerance
D ial Tone Tolerance
Tone Present D etection Time
Tone Absent D etection Time
Min Tone D uration Accept
Max Tone D uration Reject
Min. Interdigit Pause Accept
Max. Interdigit Pause Reject
Propagation D elay (St to Q)
Propagation D elay (St to StD )
Output D ata Set Up (Q to StD )
Propagation D elay (TOE to Q)
Crystal/Clock Frequency
Clock Output (OSC 2)
Capacitive
L o ad
Enable
D isable
t
DP
t
DA
t
R EC
t
R EC
t
ID
t
DO
t
PQ
t
PS
t
D
t
QS
t
D
t
PTE
t
PTD
f
CL K
C
LO
3.5759
20
13
8
3.4
200
50 0
3.5795
3.5831
30
20
40
5
0.5
±3.5%
-16
-12
+22
8
3
14
8.5
40
Symbol
Min
-36
12.3
Typ
Max
-6.4
370
6
6
1.5%±2Hz
Units
dB m
mV
RMS
dB
dB
Nom.
Nom.
dB
dB
dB
mS
mS
mS
mS
mS
µS
µS
µS
µS
nS
nS
MHz
pF
Notes
1,2,3,4,5,8
2,3,5,8,10
2,3,5
2,3,4,5,8,9,13,14
2,3,4,5,6,8,9
2,3,4,5,7,8,9
Refer to
Timing D iagram
(User Adjustable)
Times shown are
obtained with
circuit in Fig. 1)
TOE = V
DD
R
L
= 10 K
Ω
C
L
= 50pF
Notes:
1. dBm = decibels above or below a reference power
of 1 mW into a 600 ohm load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40mS. Tone pause = 40 mS.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have
an equal amplitude.
6. Bandwidth limited (0 to 3 KHz) Gaussian Noise.
7. The precise dial tone frequencies are
(350 Hz and 440 Hz) ±2%.
8. For an error rate of better than 1 in 10,000
9.
10.
11.
12.
13.
14.
Referenced to lowest level frequency component
in DTMF signal.
Minimum signal acceptance level is measured with
specified maximum frequency deviation.
Input pins defined as IN+, IN-, and TOE.
External voltage source used to bias V
REF
.
This parameter also applies to a third tone injected onto
the power supply.
Referenced to Figure 1. Input DTMF tone level
at -28 dBm.
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
CALIFORNIA MICRO DEVICES
CM88L70/70C
Explanation of Events
A)
B)
C)
D)
E)
F)
G)
Tone bursts detected, tone duration invalid, outputs not
updated.
Tone #n detected, tone duration valid, tone decoded and
latched in outputs.
End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
Outputs switched to high impedance state.
Tone #n + 1 detected, tone duration valid, tone decoded
and latched in outputs (currently high impedance).
Acceptable dropout of tone #n + 1, tone absent duration
invalid, outputs remain latched.
End of tone #n + 1 detected, tone absent duration valid,
outputs remain latched until next valid tone.
Explanation of Symbols
V
IN
ESt
St/GT
Q1-Q4
StD
DTMF composite input signal.
Early Steering Output. Indicates detection
of valid tone frequencies.
Steering input/guard time output. Drives
external RC timing circuit.
4-bit decoded tone output.
Delayed Steering Output. Indicates that
valid frequencies have been present/absent
for the required guard time, thus constituting
a valid signal.
Tone Output Enable (input). A low level
shifts Q1-Q4 to its high impedance state.
Maximum DTMF signal duration not
detected as valid.
Minimum DTMF signal duration required
for valid recognition.
Minimum time between valid DTMF signals.
Maximum allowable drop-out during valid
DTMF signal.
Time to detect the presence of valid
DTMF signals.
Time to detect the absence of valid
DTMF signals.
Guard time, tone present.
Guard time, tone absent.
TOE
t
REC
t
REC
t
ID
t
DO
t
DP
t
DA
t
GTP
t
GTA
©2000 California Micro Devices Corp. All rights reserved.
4
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8/16/2000
CALIFORNIA MICRO DEVICES
Functional Description
The CAMD CM88L70/70C DTMF Integrated Receiver provides the
design engineer with not only low power consumption, but high
performance in a small 18-pin DIP, SOIC, or 20-pin PLCC, TSSOP, or
QSOP package configuration. The CM88L70/70Cs internal
architecture consists of a bandsplit filter section which separates the
high and low tones of the received pair, followed by a digital decode
(counting) section which verifies both the frequency and duration of
the received tones before passing the resultant 4-bit code to the output
bus.
Filter Section
Separation of the low-group and high-group tones is achieved by
applying the dual-tone signal to the inputs of two 9
th
-order switched
capacitor bandpass filters. The bandwidths of these filters correspond
to the bands enclosing the low-group and high-group tones (See
Figure 3). The filter section also incorporates notches at 350 Hz and
440 Hz which provides excellent dial tone rejection. Each filter output
is followed by a single order switched capacitor section which smooths
the signals prior to limiting. Signal limiting is performed by high-gain
comparators. These comparators are provided with a hysteresis to
prevent detection of unwanted low-level signals and noise. The
outputs of the comparators provide full-rail logic swings at the
frequencies of the incoming tones.
Decoder Section
The CM88L70/70C decoder uses a digital counting technique to
determine the frequencies of the limited tones and to verify that these
tones correspond to standard DTMF frequencies. A complex averaging
algorithm is used to protect against tone simulation by extraneous
signals (such as voice) while providing tolerance to small frequency
variations. The averaging algorithm has been developed to ensure
an optimum combination of immunity to talk-off and tolerance to
the presence of interfering signals (third tones) and noise. When the
detector recognizes the simultaneous presence of two valid tones
(known as signal condition), it raises the Early Steering flag (ESt).
Any subsequent loss of signal condition will cause ESt to fall.
Steering Circuit
Before the registration of a decoded tone pair, the receiver checks for
a valid signal duration (referred to as character-recognition-
condition). This check is performed by an external RC time constant
driven by E
St
. A logic high on ESt causes V
C
(See Figure 4) to rise as
the capacitor discharges. Providing signal condition is maintained
(ESt remains high) for the validation period (t
GTP
), V
C
reaches the
threshold (V
TSt
) of the steering logic to register the tone pair, thus
latching its corresponding 4-bit code (See Figure 2) into the output
latch. At this point, the GT output is activated and drives VC to V
DD
.
GT continues to drive high as long as ESt remains high, signaling that
a received tone pair has been registered. The contents of the output
latch are made available on the 4-bit output bus by raising the three-
state control input (TOE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals. Thus, as well
as rejecting signals too short to be considered valid, the receiver will
tolerate signal interruptions (drop outs) too short to be considered a
valid pause. This capability together with the capability of selecting
the steering time constants externally, allows the designer
to tailor
performance to meet a wide variety of system requirements.
Guard Time Adjustment
In situations which do not require independent selection of receive
and pause, the simple steering circuit of Figure 4 is applicable.
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
CM88L70/70C
Component values are chosen according to the following formula:
t
REC
= t
DP
+ t
GTP
t
GTP
» 0.67 RC
The value of t
DP
is a parameter of the device and t
REC
is the minimum
signal duration to be recognized by the receiver. A value for C of 0.1
uF is recommended for most applications, leaving R to be selected by
the designer. For example, a suitable value of R for a t
REC
of 40
milliseconds would be 300K. A typical circuit using this steering
configuration is shown in Figure 1. The timing requirements for most
telecommunication applications are satisfied with this circuit. Different
steering arrangements may be used to select independently the
guardtimes for tone-present (t
GTP
) and tone absent (t
GTA
). This may
be necessary to meet system specifications which place both accept
and reject limits on both tone duration and interdigit pause.
Guard time adjustment also allows the designer to tailor system
parameters such as talk-off and noise immunity. Increasing t
REC
improves talk-off performance, since it reduces the probability that
tones simulated by speech will maintain signal condition for long
enough to be registered. On the other hand, a relatively short t
REC
with a long t
DO
would be appropriate for extremely noisy environments
where fast acquisition time and immunity to drop-outs would be
requirements. Design information for guard time adjustment is shown
in Figure 5.
Input Configuration
The input arrangement of the CM88L70/70C provides a differential
input operational amplifier as well as a bias source (V
REF
) which is
used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor to the op-
amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are connected as shown
in Figure 1, with the op-amp connected for unity gain and VREF biasing
the input at ½ V
DD
. Figure 6 shows the differential configuration,
which permits the adjustment of gain with the feedback resistor R5.
Clock Circuit
The internal clock circuit is completed with the addition of a standard
television color burst crystal or ceramic resonator having a resonant
frequency of 3.579545 MHz. The CM8870C in a PLCC package has
a buffered oscillator output (OSC3) that can be used to drive clock
inputs of other devices such as a microprocessor or other CM887Xs
as shown in Figure 7. Multiple CM88L70/70Cs can be connected as
shown in figure 8 such that only one crystal or resonator is required.
Power Down and Inhibit Mode
A logic high applied to pin 6 (PD) will power down the device to
minimize the power consumption in a standby mode. It stops the
oscillator and functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It
inhibits the detection of tones representing characters A, B, C and
D. The output code will remain the same as the previous detected
code (see Figure 2).
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
5
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