HIGH-SPEED 3.3V 16K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
x
x
IDT70V9269S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12/15ns (max.)
Low-power operation
– IDT70V9269S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9269L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-through or Pipelined output mode on either port via
the
FT/PIPE
pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
x
x
x
x
x
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all Control,
data, and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/
W
L
UB
L
CE
0L
1
0
0/1
R/
W
R
UB
R
CE
0R
CE
1L
LB
L
OE
L
1
0
0/1
CE
1R
LB
R
OE
R
FT
/PIPE
L
0/1
1b 0b
b
a
1a 0a
0a 1a
a
b
0b 1b
0/1
FT
/PIPE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
A
13L
A
0L
CLK
L
CNTEN
L
CNTRST
L
ADS
L
A
13R
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3752 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC 3752/6
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9269 is a high-speed 16K x 16 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address in-puts provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
With an input data register, the IDT70V9269 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 429mW of power.
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A
10R
A
11R
A
12R
A
13R
N/C
N/C
N/C
N/C
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
V
CC
GND
R/W
R
OE
R
FT/PIPE
R
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
V
CC
V
CC
I/O
11R
Pin Configuration
(1,2,3)
N/C
N/C
N/C
N/C
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
NC
CNTEN
R
CLK
R
ADS
R
GND
V
CC
ADS
L
CLK
L
CNTEN
L
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V9269PRF
PK-128
(4)
128-Pin TQFP
Top View
(5)
A
10L
A
11L
A
12L
A
13L
N/C
N/C
N/C
N/C
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
V
CC
GND
R/W
L
OE
L
FT/PIPE
L
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
V
CC
GND
I/O
11L
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O
10R
I/O
9R
GND
N/C
I/O
8R
N/C
N/C
I/O
7R
V
CC
I/O
6R
I/O
5R
I/O
4R
GND
I/O
3R
V
CC
I/O
2R
I/O
1R
I/O
0R
GND
V
CC
I/O
0L
I/O
1L
GND
I/O
2L
I/O
3L
GND
I/O
4L
I/O
5L
I/O
6L
I/O
7L
V
CC
N/C
N/C
I/O
8L
N/C
V
CC
I/O
9L
I/O
10L
3752 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L,
CE
1L
R/W
L
OE
L
A
0L
- A
13L
I/O
0L
- I/O
15L
CLK
L
UB
L
LB
L
ADSL
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R,
CE
1R
R/W
R
OE
R
A
0R
- A
13R
I/O
0R
- I/O
15R
CLK
R
UB
R
LB
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Upper Byte Select
Lower Byte Select
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power
Ground
3752 tbl 01
Truth Table IRead/Write and Enable Control
(1,2,3)
OE
X
X
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
CE
0
H
X
L
L
L
L
L
L
L
L
CE
1
X
L
H
H
H
H
H
H
H
H
UB
X
X
H
L
H
L
L
H
L
L
LB
X
X
H
H
L
L
H
L
L
L
R/W
X
X
X
L
L
L
H
H
H
X
Upper Byte
I/O
8-15
High-Z
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Lower Byte
I/O
0-7
High-Z
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
3752 tbl 02
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
6.42
3
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control
(1,2)
Address
X
An
An
X
Previous
Address
X
X
Ap
Ap
Addr
Used
0
An
Ap
Ap + 1
CLK
↑
↑
↑
↑
ADS
X
L
(4)
H
H
CNTEN
X
X
H
L
(5)
CNTRST
L
H
H
H
I/O
(3)
D
I/O
(0)
D
I/O
(n)
D
I/O
(p)
D
I/O
(p+1)
MODE
Counte r Reset to Address 0
External Address Loaded into Counter
External Address Blocked—Counter disabled (Ap reused)
Counter Enabled—Internal Address generation
3752 tbl 03
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB,
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
is independent of all other signals including
CE
0
, CE
1
,
UB
and
LB.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB
and
LB.
Recommended Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
3752 tbl 04
Recommend DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.2
-0.3
(1)
Typ.
3.3
0
____
Max.
3.6
0
V
CC
+0.3V
(2)
0.8
Unit
V
V
V
V
3752 tbl 05
NOTE:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter T
A
. This is the "instant on" case temperature.
____
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
CC
+ 0.3V.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to
GND
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Capacitance
(1)
(T
A
= +25°C, f = 1.0MH
z
)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3752 tbl 07
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
o
mA
3752 tbl 06
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 0.3V.
6.42
4
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
70V9269S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
CE
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
70V9269L
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3752 tbl 08
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperture and Supply Voltage Range
(3,6,7)
(V
CC
= 3.3V ± 0.3V)
70V9269X9
Com'l Only
Symbol
I
CC
Parameter
Dynamic
Operating
Current (Both
Ports Active)
Standby
Current (Both
Ports - TTL
Level Inputs)
Standby
Current (One
Port - TTL
Level Inputs)
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Full Standby
Current (One
Port - CMOS
Level Inputs)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
Version
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(4)
180
180
____
____
70V9269X12
Com'l Only
Typ.
(4)
150
150
____
____
70V9269X15
Com'l Only
Typ.
(4)
130
130
____
____
Max.
260
225
____
____
Max.
240
205
____
____
Max.
220
185
____
____
Unit
mA
I
SB1
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
50
50
____
____
75
65
____
____
40
40
____
____
65
50
____
____
30
30
____
____
55
35
____
____
mA
I
SB2
COM'L
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
IND
f=f
MAX
(1)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port,
Outputs Disable d, f = f
MAX
(1)
COM'L
IND
COM'L
IND
110
110
____
____
170
150
____
____
100
100
____
____
160
140
____
____
90
90
____
____
150
130
____
____
mA
I
SB3
1.0
0.4
____
____
5
3
____
____
1.0
0.4
____
____
5
3
____
____
1.0
0.4
____
____
5
3
____
____
mA
I
SB4
100
100
____
____
160
140
____
____
90
90
____
____
150
130
____
____
80
80
____
____
140
120
____
____
mA
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, T
A
= 25°C for Typ, and are not production tested. I
CC DC
(f=0) = 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
CC
- 0.2V means
CE
0X
> V
CC
- 0.2V or CE
1X
< 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
3752 tbl 09
6.42
5
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