DATA SHEET
Integrated
ICS843034-01
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY
ICS843034-01
Circuit
F
EMTO
C
LOCKS
™
Systems, Inc.
SYNTHESIZER
PRELIMINARY
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs which can be set
independently for either 3.3V or 2.5V
•
4:1 Input Mux:
1 differential input
1 single-ended input
2 crystal oscillator interfaces
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
TEST_CLK accepts LVCMOS or LVTTL input levels
•
Output frequency range: 30.625MHz to 640MHz
•
Crystal input frequency range: 12MHz to 40MHz
•
VCO range: 490MHz to 640MHz
•
Parallel or serial interface for programming feedback divider
and output dividers
•
RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637kHz to 5MHz): 0.61ps (typical)
•
Supply voltage modes:
LVPECL outputs (core/outputs):
3.3V/3.3V
3.3V/2.5V
REF_CLK output (core/outputs):
3.3V/3.3V
3.3V/2.5V
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS843034-01 is a general purpose, low
phase noise LVPECL synthesizer which can
HiPerClockS™
generate frequencies for a wide variety of
applications. The ICS843034-01 has a 4:1
input Multiplexer from which the following
inputs can be selected: 1 differential input, 1
single-ended input, or one of two crystal oscillators,
thus making the device ideal for frequency translation or
generation. Each differential LVPECL output pair has an
output divider which can be independently set so that two
different frequencies can be generated. Additionally, each
LVPECL output pair has a dedicated power supply pin so
the outputs can run at 3.3V or 2.5V. The ICS843034-01
also supplies a buffered copy of the reference clock or
crystal frequency on the single-ended REF_CLK pin which
can be enabled or disabled (disabled by default). The output
frequency can be programmed using either a serial or
parallel programming interface.
IC
S
The ICS843034-01 has excellent <1ps phase jitter
performance over the 637kHz - 5MHz integration range, thus
making it suitable for use in Fibre Channel, SONET, and
Ethernet/1Gb Ethernet applications.
Example applications include systems which must support
both FEC and non FEC rates. In 10Gb Fibre Channel, for
example, you can use a 25.5MHz crystal to generate a
159.375MHz reference clock, and then switch to a
20.544MHz crystal to generate 164.355MHz for 66/64 FEC.
Other applications could include supporting both Ethernet
frequencies and SONET frequencies in an application. When
Ethernet frequencies are needed, a 25MHz crystal can be
used and when SONET frequencies are needed, the input
MUX can be switched to select a 38.88MHz Crystal.
P
IN
A
SSIGNMENT
M8
NB0
NB1
NB2
OE_REF
OE_A
OE_B
V
CC
NA0
NA1
NA2
V
EE
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
48-Pin LQFP
6
31
7mm x 7mm x 1.4mm
7
30
package body
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843034AY
-01
IDT™ / ICS™
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
1
1
CLK
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
M5
M6
M7
ICS843034-01
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
TEST_CLK
SEL1
SEL0
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
V
EE
P_DIV
V
CCO
_
REF
REF_CLK
V
CCO
_
B
nFOUTB0
FOUTB0
V
CCO
_
A
nFOUTA0
FOUTA0
V
CC
TEST
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
ICS843034-01
PRELIMINARY
ICS843034-01
Circuit
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Integrated
ICS843034-01
Systems, Inc.
F
EMTO
C
LOCKS
™
TSD
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
B
LOCK
D
IAGRAM
OE_A
VCO_SEL
XTAL_IN0
XTAL_OUT0
OSC
00
XTAL_IN1
OSC
XTAL_OUT1
CLK
nCLK
TEST_CLK
SEL1
SEL0
P_DIV
OE_B
MR
01
P
HASE
10
11
1
÷
4
0
÷8
D
ETECTOR
VCO
0
1
÷1
÷2
÷3
÷4
÷5
101
÷6
÷8
111
÷16
÷
000
001
010
011
FOUTA0
nFOUTA0
V
CCO_A
001
011
V
CCO_B
FOUTB0
nFOUTB0
÷M
101
111
÷16
÷
V
CCO_REF
REF_CLK
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M8:M0
NA2:NA0
NB2:NB0
C
TEST
I
L
843034AY-01
www.icst.com/products/hiperclocks.html
2
REV. C NOVEMBER 28, 2005
IDT™ / ICS™
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
2
ICS843034-01
PRELIMINARY
ICS843034-01
Circuit
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Integrated
ICS843034-01
Systems, Inc.
F
EMTO
C
LOCKS
™
TSD
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
Nx bits can be hardwired to set the M divider and Nx output
divider to a specific default state that will automatically occur
during power-up. The TEST output is LOW when operating in
the parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
fVCO = fxtal x M
P
The M value and the required values of M0 through M5 are shown
in Table 3B to program the VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 20
≤
M
≤
25. The frequency out is de-
fined as follows:
FOUT = fVCO = fxtal x M
N
NxP
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and Nx output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and Nx output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and Nx
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and Nx bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Output
Output of M divider
CMOS Fout A0
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS843034-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 490MHz to 640MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS843034-01 supports either serial or parallel program-
ming modes to program the M feedback divider and N output
divider. The input divider P can only be changed using the P_DIV
pin. It cannot be changed from the default
÷1
setting using the
serial interface.
Figure 1
shows the timing diagram for each mode.
In parallel mode, the nP_LOAD input is initially LOW. The data
on the M, NA, and NB inputs are passed directly to the M di-
vider and both N output dividers. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M and N
dividers remain loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and
S
ERIAL
L
OADING
S_CLOCK
S_DATA
T1
T0
NB2
NB1 NB0
NA2
NA1
NA0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
H
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, P_DIV,
NA0:NA2, NB0:NB2
nP_LOAD
M, N, P
t
S
t
H
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
843034AY
-01
www.icst.com/products/hiperclocks.html
3
REV. C NOVEMBER 28, 2005
IDT™ / ICS™
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
3
ICS843034-01
PRELIMINARY
ICS843034-01
Circuit
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Integrated
ICS843034-01
Systems, Inc.
F
EMTO
C
LOCKS
™
TSD
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23
Name
M8
NB0, NB1
NB2
OE_REF
OE_A
OE_B
V
CC
NA0, NA1
NA2
V
EE
TEST
FOUTA0,
nFOUTA0
V
CCO_A
FOUTB0,
nFOUTB0
V
CCO_B
REF_CLK
V
CCO_REF
P_DIV
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Output
Power
Output
Power
Output
Power
Input
Pullup/
Pulldown
Pullup
Type
Description
M divider input. Data latched on LOW-to-HIGH trnsition of nP_LOAD
Pulldown
input. LVCMOS/LVTTL interfac levels.
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS/LVTTL interface levels.
Pulldown
Output enable. Controls enabling and disabling of REF_CLK output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
Core supply pins.
Pulldown
Pullup
Pullup
Determines output divider value as defined in Table 3C,
Pulldown Function Table. LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_CLK.
Input divide select. Float = ÷1 (default), 1 =
÷
4, 0 = ÷8.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
inver ted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Asser tion of MR does not
affect loaded M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
25
MR
Input
Pulldown
26
27
28
29
30, 31
32
33, 34
35, 36
37
38
S_CLOCK
S_DATA
S_LOAD
V
CCA
SEL0, SEL1
TEST_CLK
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
XTAL_OUT1
CLK
nCLK
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Cr ystal oscillator interface.
Cr ystal oscillator interface.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input.V
CC
/2 default when left floating.
Pulldown
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4
REV. C NOVEMBER 28, 2005
Continued on next page...
843034AY-01
IDT™ / ICS™
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
4
ICS843034-01
PRELIMINARY
ICS843034-01
Circuit
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Integrated
ICS843034-01
Systems, Inc.
F
EMTO
C
LOCKS
™
TSD
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
Number
39
Name
nP_LOAD
Input
Type
40
41, 42, 43,
44, 45, 47, 48
46
VCO_SEL
M0, M1, M2,
M3, M4, M6, M7
M5
Input
Input
Input
Description
Parallel load input. Determines when data present at M5:M0 is
loaded into M divider, and when data present at NA2:NA0 and
Pulldown
NB2:NB0 is loaded into the N output dividers.
LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS/LVTTL interface levels.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
Test Conditions
Minimum
Typical
4
51
51
7
12
Maximum
Units
pF
kΩ
kΩ
Ω
843034AY
-01
www.icst.com/products/hiperclocks.html
5
REV. C NOVEMBER 28, 2005
IDT™ / ICS™
FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
5
ICS843034-01
嵌入式系统
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