1CY7C225A
CY7C225A
512 x 8 Registered PROM
Features
• CMOS for optimum speed/power
• High speed
— 25 ns address set-up
— 12 ns clock to output
• Low power
— 495 mW (Commercial)
•
•
•
•
•
•
•
•
— 660 mW (Military)
Synchronous and asynchronous output enables
On-chip edge-triggered registers
Buffered common PRESET and CLEAR inputs
EPROM technology, 100% programmable
Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC,
or 28-pin PLCC
5V
±10%
V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C225A is a high-performance 512-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, and 28-pin PLCC. The memory cells utilize proven
EPROM floating gate technology and byte-wide intelligent
programming algorithms.
The CY7C225A replaces bipolar devices and offers the advan-
tages of lower power, superior performance, and high
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that
after customer programming the product will meet AC specifi-
cation limits.
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
ADDRESS
O
2
O
1
ADDRESS
DECODER
8-BIT
EDGE-
TRIGGERED
REGISTER
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
O
5
O
4
O
7
Pin Configurations
DIP
Top View
A
7
O
6
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
3
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
PS
E
CLR
E
S
CP
O
7
O
6
O
5
O
4
O
3
CLR
CP
A
4
A
3
A
2
A
1
A
0
NC
O
0
E
S
E
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 13 141516 17 18
O1
O2
GND
NC
O3
O4
O5
A5
A6
A7
NC
VCC
A8
PS
E
CLR
E
S
CP
NC
O
7
O
6
PS
S
R
CP
O
0
LCC/PLCC
Top View
Selection Guide
7C225A-25
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating
Current
Commercial
Military
25
12
90
7C225A-30
30
15
90
120
7C225A-40
40
25
Unit
ns
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-04001 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised October 8, 2002
CY7C225A
Maximum Ratings
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................−0.5V
to +7.0V
DC Input Voltage
.................................................−3.0V
to +7.0V
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Military
[2]
Ambient
Temperature
0
°
C to +70
°
C
−55
°
C to +125
°
C
V
CC
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
[3,4]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
V
CD
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Leakage Current
Input Clamp Diode Voltage
Output Leakage Current
Output Short Circuit Current
Power Supply Current
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
IN
= V
IH
or V
IL
V
CC
= Min., I
OL
= 16 mA
V
IN
= V
IH
or V
IL
Guaranteed Input Logical HIGH Voltage for
All Inputs
Guaranteed Input Logical LOW Voltage for All
Inputs
GND < V
IN
< V
CC
Note 4
GND < V
OUT
< V
CC
, Output Disabled
[5]
V
CC
= Max., V
OUT
= 0.0V
[6]
I
OUT
= 0 mA
V
CC
= Max.
Commercial
Military
12
−10
−20
+10
−90
90
120
13
50
3.0
0.4
V
mA
V
V
µA
mA
mA
−10
2.0
0.8
+10
Min.
2.4
0.4
Max.
Unit
V
V
V
V
µA
V
PP
I
PP
V
IHP
V
ILP
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming
Voltage
Input LOW Programming
Voltage
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
=5.0V
Max.
10
10
Unit
pF
pF
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04001 Rev. *B
Page 2 of 9
CY7C225A
AC Test Loads and Waveforms
[4]
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
167Ω
R1 250Ω
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
R2
167Ω
R1 250Ω
ALL INPUT PULSES
3.0V
GND
< 5 ns
90%
10%
90%
10%
< 5 ns
(a) NormalLoad
Equivalent to:
THÉVENIN EQUIVALENT
100Ω
(b) High Z Load
OUTPUT
2.0V
Operating Modes
The CY7C225A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (E
S
) and asynchronous (E) output
enables and CLEAR and PRESET inputs.
Upon power-up, the synchronous enable (E
S
) flip-flop will be
in the set condition causing the outputs (O
0
−O
7
) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address inputs (A
0
−A
8
) and a logic
LOW to the enable (E
S
) input. The stored data is accessed and
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O
0
−O
7
) provided the asynchronous enable (E) is
also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the synchronous enable (E
S
) input is switched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C225A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C225A has buffered asynchronous CLEAR and
PRESET inputs. Applying a LOW to the PRESET input causes
an immediate load of all ones into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). Applying a LOW to the CLEAR input,
resets the flip-flops to all zeros. The initialize data will appear
at the device outputs after the outputs are enabled by bringing
the asynchronous enable (E) LOW.
When power is applied, the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the E
S
input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
Document #: 38-04001 Rev. *B
Page 3 of 9
CY7C225A
Switching Characteristics
Over the Operating Range
[3,4]
7C225A-25
Parameter
t
SA
t
HA
t
CO
t
PWC
t
SES
t
HES
t
DP
, t
DC
t
RP
, t
RC
t
PWP
, t
PWC
t
COS
t
HZC
t
DOE
t
HZE
Description
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Valid Output
Clock Pulse Width
E
S
Set-Up to Clock HIGH
E
S
Hold from Clock HIGH
Delay from PRESET or CLEAR
to Valid Output
PRESET or CLEAR Recovery to
Clock HIGH
PRESET or CLEAR Pulse Width
Valid Output from Clock HIGH
[7]
Inactive Output from Clock
HIGH
[7]
Valid Output from E LOW
Inactive Output from E HIGH
15
15
20
20
20
20
10
10
0
20
20
20
20
20
20
20
Min.
25
0
12
15
10
5
20
20
20
30
30
30
30
Max.
7C225A-30
Min.
30
0
15
20
10
5
20
Max.
7C225A-40
Min.
40
0
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
7. Applies only when the synchronous (E
S
) function is used.
Switching Waveforms
[4]
t
HA
A
0
−
A
10
t
SES
E
S
t
SES
t
HES
t
HES
t
SES
t
HES
t
SA
t
HA
CP
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
O
0
−
O
7
t
CO
t
HZC
t
COS
t
CO
t
HZE
t
DOE
E
t
DP
t
DC
PS or CLR
t
PWP
t
PWC
t
RP
t
RC
,
Document #: 38-04001 Rev. *B
Page 4 of 9
CY7C225A
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
Table 1. Mode Selection
Pin Function
[8]
Read or Output Disable
Mode
Read
Output Disable
Output Disable
Clear
Preset
Program
Program Verify
Program Inhibit
Intelligent Program
Blank Check
Note:
8. X = “don’t care” but not to exceed V
CC
±5%.
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
A
8
–A
0
A
8
–A
0
A
8
–A
0
A
8
–A
0
A
8
–A
0
A
8
–A
0
A
8
–A
0
A
8
–A
0
A
8
–A
0
A–A
0
A
8
–A
0
A
8
–A
0
CP
PGM
X
X
X
X
X
V
ILP
V
IHP
V
IHP
V
ILP
V
IHP
E
S
VFY
V
IL
V
IH
X
V
IL
V
IL
V
IHP
V
ILP
V
IHP
V
IHP
V
ILP
CLR
V
PP
V
IH
V
IH
V
IH
V
IL
V
IH
V
PP
V
PP
V
PP
V
PP
V
PP
E
E
V
IL
X
V
IH
V
IL
V
IL
V
IHP
V
IHP
V
IHP
V
IHP
V
IHP
PS
PS
V
IH
V
IH
V
IH
V
IH
V
IL
V
IHP
V
IHP
V
IHP
V
IHP
V
IHP
O
7
−O
0
D
7
−D
0
O
7
−O
0
High Z
High Z
Zeros
Ones
D
7
−D
0
O
7
−O
0
High Z
D
7
−D
0
Zeros
Other
DIP
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
PS
E
V
PP
VFY
PGM
D
7
D
6
D
5
D
4
D
3
A
4
A
3
A
2
A
1
A
0
NC
D
0
LCC/PLCC
Top View
A5
A6
A7
NC
V
CC
A8
PS
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 1314151617 18
D1
D2
GND
NC
D3
D4
D5
E
V
PP
VFY
PGM
NC
D
7
D
6
Figure 1. Programming Pinouts
Document #: 38-04001 Rev. *B
Page 5 of 9
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