YC324 (8Pin/4R; Pb Free)
ARRAY CHIP RESISTORS
sizes 1220
DATA SHEET
5%, 1%
Product specification –Feb 22, 2005 V.1
Supersedes Date of Mar. 06, 2003
Product specification
2
8
Chip Resistor Surface Mount
YC
SERIES
324 (Pb Free)
SCOPE
This specification describes YC324 series chip resistor arrays with lead-free terminations made by thick film
process.
ORDERING INFORMATION
Part number is identified by the series, size, tolerance, packing type, temperature coefficient, taping reel and
resistance value.
YAGEO ORDERING CODE
CTC
CODE
O
RDERING EXAMPLE
(4)
(5)
(6)
YC324 – X X X XX XXXX L
(1) (2) (3)
(1) TOLERANCE
F = ±1%
J = ±5%
The ordering code of a YC324 convex chip resistor
array, value 1,000
X
with ±5% tolerance, supplied in
7-inch tape reel is: YC324-JK-071KL.
NOTE
(2) PACKAGING TYPE
K = Embossed taping reel
1. The “L” at the end of the code is only for ordering. On the reel
label, the standard CTC will be mentioned an additional stamp
“LFP”= lead free production.
2. Products with lead in terminations fulfil the same requirements
as mentioned in this datasheet.
3. Products with lead in terminations will be phased out in the
coming months (before July 1st, 2006)
(3) TEMPERATURE COEFFICIENT OF RESISTANCE
– = Base on spec
(4) TAPING REEL
07 = 7 inch dia. Reel
(5) RESISTANCE VALUE
56R, 560R, 5K6, 56K, 1M
(6) RESISTOR TERMINATIONS
L = Lead free terminations (pure Tin)
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Feb 22, 2005 V.1
Product specification
3
8
Chip Resistor Surface Mount
YC
SERIES
324 (Pb Free)
MARKING
YC324
2
YNSC031
E-24 series: 3 digits
First two digits for significant figure and 3rd digit for number of zeros
Fig. 1
Value = 240 KΩ
For marking codes, please see EIA-marking code rules in data sheet “Chip resistors marking”.
CONSTRUCTION
The resistors are constructed out of
a high-grade ceramic body. Internal
metal electrodes are added at each
end and connected by a resistive
paste. The composition of the paste
is adjusted to give the approximate
required resistance and laser cutting
of this resistive layer that achieves
Fig. 2
Chip resistor construction
tolerance trims the value. The
resistive layer is covered with a
protective coat. Finally, the eight external terminations (pure Tin) are added. See fig. 2.
DIMENSIONS
Table 1
TYPE
B (mm)
H (mm)
P (mm)
L (mm)
H
2
(mm)
T (mm)
W
1
(mm)
W
2
(mm)
YC324
0.50 ±0.20
1.10 ±0.15
1.27 ±0.05
5.08 ±0.20
0.90 ±0.15
CCB257_b
protective coat
resistor layer
inner electrode
end termination
ceramic substrate
YNSC053
H
B
a
T
W1
W2
P
L
a
0.60 ±0.10
0.50 ±0.15
3.20 ±0.20
H
2
Fig. 3
YC324 series chip resistors dimension
For dimension see Table 1
SCHEMATIC
For dimension see Fig. 3 and Table 1
8
7
6
5
handbook, 2 columns
R1
R2
R3
R4
CCA862_c
Fig. 4
Equivalent circuit diagram
R1=R2=R3=R4
1
2
3
4
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Feb 22, 2005 V.1
Product specification
4
8
Chip Resistor Surface Mount
YC
SERIES
324 (Pb Free)
ELECTRICAL CHARACTERISTICS
Table 2
CHARACTERISTICS
Operating Temperature Range
Maximum Working Voltage
Maximum Overload Voltage
Dielectric Withstanding Voltage
Number of Resistors
Resistance Range
Temperature Coefficient
YC324 1/8 W
–55 °C to +155 °C
200 V
500 V
500 V
4
5% (E24) 10
Ω
to 1 MΩ
1% (E24/E96) 10
Ω
to 1 MΩ
±200 ppm/°C
FOOTPRINT AND SOLDERING
PROFILES
For recommended footprint and
soldering profiles, please see the
special data sheet “Chip resistors
mounting”.
ENVIRONMENTAL DATA
For material declaration
information (IMDS-data) of the
products, please see the
separated info “Environmental
data" conformed to EU RoHS.
PACKING STYLE AND PACKAGING QUANTITY
Table 3
Packing style and packaging quantity
PRODUCT TYPE
YC324
NOTE
PACKING STYLE
Embossed taping reel (K)
REEL DIMENSION
7" (178 mm)
QUANTITY PER REEL
4,000 units
1. For embossed tape and reel specification/dimensions, please see the special data sheet “Packing” document.
FUNCTIONAL DESCRIPTION
POWER RATING
YC324 rated power at 70°C is 1/8 W
R
ATED VOLTAGE
The DC or AC (rms) continuous working voltage
corresponding to the rated power is determined by
the following formula:
V =
√(P
X R)
Where
V = Continuous rated DC or
AC (rms) working voltage (V)
P = Rated power (W)
R = Resistance value (X)
Pmax
(%Prated)
100
MRA632
50
0
−55
0
50 70
155
100
Tamb (°C)
Fig. 5
Maximum dissipation (P
max
) in percentage of rated power
as a function of the operating ambient temperature (T
amb
)
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Feb 22, 2005 V.1
Product specification
5
8
Chip Resistor Surface Mount
YC
SERIES
324 (Pb Free)
TESTS AND REQUIREMENTS
Table 4
Test condition, procedure and requirements
TEST
Temperature
Coefficient of
Resistance
(T.C.R.)
TEST METHOD
MIL-STD-202F-method 304;
JIS C 5202-4.8
PROCEDURE
At +25/–55 °C and +25/+125 °C
REQUIREMENTS
Refer to table 2
Formula:
R
2
– R
1
T.C.R = ------------------------- × 10
6
(ppm/°C)
R
1
(t
2
– t
1
)
Where
t
1
= +25 °C or specified room temperature
t
2
= –55 °C or +125 °C test temperature
R
1
= resistance at reference temperature in ohms
R
2
= resistance at test temperature in ohms
Thermal Shock
MIL-STD-202F-method 107G;
IEC 60115-1 4.19
At –65 (+0/–10) °C for 2 minutes and at +155
(+10/–0) °C for 2 minutes; 25 cycles
At –65 (+0/–5) °C for 1 hour; RCWV applied for
45 (+5/–0) minutes
±(0.5% +0.05
Ω)
for 1% tol.
±(1.0% +0.05
Ω)
for 5% tol.
±(0.5% +0.05
Ω)
for 1% tol .
±(1.0% +0.05
Ω)
for 5% tol.
No visible damage
Low
Temperature
Operation
MIL-R-55342D-Para 4.7.4
Short Time
Overload
MIL-R-55342D-Para 4.7.5;
IEC 60115-1 4.13
2.5 × RCWV applied for 5 seconds at room
temperature
±(1.0% +0.05
Ω)
for 1% tol.
±(2.0% +0.05
Ω)
for 5% tol.
No visible damage
Insulation
Resistance
MIL-STD-202F-method 302;
IEC 60115-1 4.6.1.1
RCOV for 1 minute
≥10
GΩ
Type
Voltage (DC)
YC324
500 V
Dielectric
Withstand
Voltage
MIL-STD-202F-method 301;
IEC 60115-1 4.6.1.1
Maximum voltage (V
rms
) applied for 1 minute
No breakdown or flashover
Type
Voltage (AC)
YC324
500 V
rms
±(0.5% +0.05
Ω)
for 1% tol.
±(1.0% +0.05
Ω)
for 5% tol.
No visible damage
Resistance to
Soldering
Heat
MIL-STD-202F-method 210C;
IEC 60115-1 4.18
Unmounted chips; 260 ±5 °C for 10 ±1 seconds
Life
MIL-STD-202F-method 108A;
IEC 60115-1 4.25.1
At 70 ±2 °C for 1,000 hours; RCWV applied for
1.5 hours on and 0.5 hour off
±(1% +0.05
Ω)
for 1% tol.
±(3% +0.05
Ω)
for 5% tol.
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Feb 22, 2005 V.1