CY29949
2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer
Features
• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible outputs
• 15 clock outputs: drive up to 30 clock lines
• 1X and 1/2X configurable outputs
• Output three-state control
• 350 ps max. output-to-output skew
• Pin compatible with MPC949, MPC9449
• Available in Commercial and Industrial temp. range
• 52-pin TQFP package
Description
The CY29949 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources can be used to provide for test clocks as well as the
primary system clocks. All other control inputs are
LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or
LVTTL compatible and can drive 50Ω series or parallel termi-
nated transmission lines. For series terminated transmission
lines, each output can drive one or two traces giving the device
an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
Block Diagram
Pin Configuration
TCLK_SEL
NC
VDDC
QB2
VSS
QB1
VDDC
QB0
VSS
VSS
QA1
VDDC
QA0
VSS
0
1
0
1
R
1
2
PECL_CLK
PECL_CLK#
PECL_SEL
DSELA
0
1
2
52 51 50 49 48 47 46 45 44 43 42 41 40
QA(0:1)
1
R
2
0
1
3
QB(0:2)
DSELB
1
R
2
0
1
4
QC(0:3)
DSELC
1
R 2
0
1
6
QD(0:5)
MR/OE#
TCLK_SEL
VDD
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
CY29949
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
DSELD
MR/OE#
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
VDDC
QD4
VSS
QD3
VDDC
QD2
VSS
QD1
VDDC
QD0
VSS
NC
Cypress Semiconductor Corporation
Document #: 38-07289 Rev. *D
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised November 6, 2003
CY29949
Pin Description
[1]
Pin
6
7
4, 5
49, 51
42, 44, 46
Name
PECL_CLK
PECL_CLK#
TCLK(0,1)
QA(1,0)
QB(2:0)
VDDC
VDDC
VDDC
VDDC
PWR
I/O
I, PD
PECL Input Clock
I, PU
PECL Input Clock
I, PU
External Reference/Test Clock Input
O
O
O
O
Clock Outputs
Clock Outputs
Clock Outputs
Clock Outputs
Description
31, 33, 35, 37 QC(3:0)
16, 18, 20, 22, QD(5:0)
24, 28
9, 10, 11, 12
2
8
1
DSEL(A:D)
TCLK_SEL
PCLK_SEL
MR/OE#
I, PD
Divider Select Inputs.
When HIGH, selects
÷2
input divider. When LOW,
selects
÷1
input divider.
I, PD
TCLK Select Input.
When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
I, PD
PECL Select Input.
When HIGH, PECL clock is selected and when LOW
TCLK(0,1) is selected
I, PD
Output Enable Input.
When asserted LOW, the outputs are enabled and
when asserted HIGH, internal flip-flops are reset and the outputs are
three-stated. If more than 1 bank is being used in /2 mode, a reset must
be performed (MR/OE# asserted high) after power-up to ensure that all
internal flip flops are set to the same state.
2.5V or 3.3V Power Supply for Output Clock Buffers
2.5V or 3.3V Power Supply
Common Ground
17, 21, 25, 32, VDDC
36, 41, 45, 50
3
VDD
13, 15, 19, 23, VSS
29, 30, 34, 38,
43, 47, 48, 52
14, 26, 27, 39, NC
40,
Note:
1. PD = internal pull-down, PU = internal pull-up.
Not Connected
Document #: 38-07289 Rev. *D
Page 2 of 7
CY29949
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............ V
SS
– 0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD Protection............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
(V
DD
= V
DDC
= 3.3V ±10% or 2.5V ±5%, over the specified temperature range)
Parameter
V
IL
Description
Input Low Voltage
Conditions
V
DD
= 3.3V, PECL_CLK single ended
V
DD
= 2.5V, PECL_CLK single ended
All other inputs
V
IH
Input High Voltage
V
DD
= 3.3V, PECL_CLK single ended
V
DD
= 2.5V, PECL_CLK single ended
All other inputs
I
IL
I
IH
V
PP
V
CMR
V
OL
V
OH
I
DDQ
I
DD
Input Low Current
[3]
Min.
1.49
1.10
V
SS
2.135
1.75
2.0
–
–
300
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
5
200
330
140
235
15
18
4
Max.
1.825
1.45
0.8
2.42
2.0
V
DD
–100
100
1000
V
DD
– 0.6
V
DD
– 0.6
0.4
–
–
7
–
–
–
–
18
22
–
Unit
V
V
µA
mV
V
V
V
mA
mA
Input High Current
[3]
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
[4]
PECL_CLK
Output Low Voltage
[5]
Output High Voltage
[5]
Quiescent Supply Current
Dynamic Supply Current
V
DD
= 3.3V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 3.3V, Outputs @ 160 MHz,
CL = 30 pF
V
DD
= 2.5V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 2.5V, Outputs @ 160 MHz,
CL = 30 pF
V
DD
= 3.3V
V
DD
= 2.5V
I
OL
= 20 mA
I
OH
= –20 mA, V
DD
= 3.3V
I
OH
= –20 mA, V
DD
= 2.5V
V
DD
– 2.0
V
DD
– 1.2
–
2.5
1.8
–
–
–
–
–
12
14
–
Zout
C
in
Output Impedance
Input Capacitance
V
DD
= 3.3V
V
DD
= 2.5V
Ω
pF
Notes:
2.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
CMR
range
and the input lies within the V
PP
specification.
5. Driving series or parallel terminated 50Ω (or 50Ω to V
DD
/2) transmission lines.
Document #: 38-07289 Rev. *D
Page 3 of 7
CY29949
AC Parameters
(V
DD
= V
DDC
= 3.3V ±10% or 2.5V ±5%, over the specified temperature range)
[6]
Parameter
Fmax
Tpd
Input
Description
Frequency
[7]
Conditions
V
DD
= 3.3V
V
DD
= 2.5V
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
[7]
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
[7]
FoutDC
tpZL, tpZH
tpLZ, tpHZ
Tskew
Tskew(pp)
Tr/Tf
Output Duty
Cycle
[7, 8]
Measured at VDD/2
Output Enable Time (all outputs)
Output Disable Time (all outputs)
Output-to-Output Skew
[7, 9]
Part-to-Part Skew
[10]
Output Clocks Rise/Fall Time
[9]
PECL_CLK to Q
TCLK to Q
0.8V to 2.0V,
V
DD
= 3.3V
0.6V to 1.8V,
V
DD
= 2.5V
V
DD
= 2.5V
V
DD
= 3.3V
Min.
–
–
4.0
4.2
6.0
6.2
45
2
2
–
–
–
0.10
0.10
Typ.
–
–
–
–
–
–
–
–
–
250
1.5
2.0
–
–
Max.
200
170
8.6
10.5
10.6
10.5
55
10
10
350
2.75
4.0
1.0
1.3
ns
%
ns
ns
ps
ns
ns
Unit
MHz
CY29949 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29949 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
CY29949 DUT
Zo = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 2. PECL_CLK CY29949 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. See
Figures 1 and 2.
10. Part-to-Part skew at a given temperature and voltage.
Document #: 38-07289 Rev. *D
Page 4 of 7
CY29949
PECL_CLK
PECL_CLK
V
PP
V
CMR
VCC
Q
VCC /2
t
PD
GND
Figure 3. Propagation Delay (TPD) Test Reference
LVCMOS_CLK
VCC
VCC /2
GND
VCC
Q
VCC /2
t
PD
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
VCC
VCC /2
t
P
T0
GND
DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (FoutDC)
VCC
VCC /2
GND
VCC
VCC /2
t
SK(0)
Figure 6. Output-to-Output Skew tsk(0)
GND
Ordering Information
Part Number
CY29949AI
CY29949AIT
CY29949AC
CY29949ACT
Package Type
52 Pin TQFP
52 Pin TQFP - Tape and Reel
52 Pin TQFP
52 Pin TQFP - Tape and Reel
Production Flow
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
Commercial, 0°C to +70°C
Commercial, 0°C to +70°C
Document #: 38-07289 Rev. *D
Page 5 of 7
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