• Three copies configurable PCI free-running clocks
• Two 48 MHz clocks (USB, DOT)
• Five/six copies of 3V66 clocks
Table 1. Frequency Table
[1]
S2
1
1
0
0
M
S1
0
1
0
1
0
CPU (1:2)
100M
133M
100M
133M
TCLK/2
3V66
66M
66M
66M
66M
TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66M
66M
TCLK/4
66IN/3V66–5
66-MHz clock input
66-MHZ clock input
66M
66M
TCLK/4
PCIF, PCI
66IN/2
66IN/2
33 M
33 M
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
TCLK
USB/ DOT
48M
48M
48M
48M
TCLK/2
One VCH clock
One reference clock at 14.318 MHz
SMBus support with read-back capabilities
Ideal Lexmark profile Spread Spectrum electromag-
netic interference (EMI) reduction
• Dial-a-Frequency™ features
• Dial-a-dB™ features
• 48-pin TSSOP package
•
•
•
•
Block Diagram
X1
X2
Pin Configuration
VDD_REF
PWR
XTAL
OSC
REF
XIN
XOUT
GND_REF
VDD_CPU
CPUT1:2
CPUC1:2
VDD_PCI
PCIF
Stop
Clock
Control
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
VDD_REF
REF
S1
CPU_STOP#
VDD_CPU
CPUT1
CPUC1
GND_CPU
VDD_CPU
CPUT2
CPUC2
IREF
S2
USB_48MHz
DOT_48MHz
VDD_48 MHz
GND_48 MHz
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_3V66
GND_3V66
SCLK
SDATA
PLL Ref Freq
PLL 1
S1:2
VTT_PWRGD##
CPU_STOP#
Gate
Divider
Network
PWR
Stop
Clock
Control
PCI7
PCI8
PCIF
GND_PCI
PCI0
PCI1
PCI2
VDD_PCI
PCI4
PCI5
PCI6
VDD_3V66
GND_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66BUFF2/3V66_4
66IN/3V66_5
PD#
VDD_CORE
GND_CORE
VTT_PWRGD#
PWR
PCI0:2
PCI4:8
CY28339
PCI_STOP#
PD#
PWR
37
36
35
34
33
32
31
30
29
28
27
26
25
/2
VDD_3V66
3V66_0:1
PWR
3V66_2:4/
66BUFF0:2
3V66_5/ 66IN
PLL 2
VDD_48MHz
PWR
USB (48MHz)
DOT (48MHz)
VCH_CLK/ 3V66_1
SDATA
SCLK
SMBus
Logic
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up,
a 0 state will be latched into the device’s internal state register.
Cypress Semiconductor Corporation
Document #: 38-07507 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 25, 2004
[+] Feedback
CY28339
Pin Definitions
Pin Number
47
1
2
43, 42,
39, 38
29
31
20
17, 18, 19
6
8, 9, 10, 12, 13,
14, 4, 5
35
34
36
46
37
21
30
45
24
REF0
XIN
XOUT
CPUT1,CPUC1
CPUT2, CPUC2
3V66_0
3V66_1/VCH
66IN/3V66_5
66BUFF [2:0]
/3V66 [4:2]
PCIF
PCI [0:2]
PCI [4:6]
PCI [7:8]
USB_48M
DOT_48M
S2
S1
IREF
PD#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
Name
I/O
3.3V 14.318-MHz clock output.
14.318-MHz crystal input.
14.318-MHz crystal input.
Differential CPU clock outputs.
3.3V 66-MHz clock output.
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal
VCO.
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO.
33 MHz clocks divided down from 66Input or divided down from 3V66;
PCIF
default is free-running.
PCI clock outputs divided down from 66Input or divided down from 3V66;
PCI [7:8] are configurable as free-running PCI through SMBus.
[2]
Fixed 48-MHz clock output.
Fixed 48-MHz clock output.
Special 3.3V three-level input for Mode selection.
3.3V LVTTL inputs for CPU frequency selection.
A precision resistor is attached to this pin which is connected to the
internal current reference.
3.3V LVTTL input for Power_Down# (active LOW).
3.3V LVTTL input for PCI_STOP# (active LOW).
3.3V LVTTL input for CPU_STOP# (active LOW).
3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1]
inputs are valid and OK to be sampled (Active LOW).
Once VTT_PWRGD#
is sampled LOW, the status of this input will be ignored.
SMBus-compatible SDATA.
SMBus-compatible SCLK.
3.3V power supply for outputs.
Description
25
26
11, 15, 28, 40, 44,
48
SDATA
SCLK
VDD_PCI,
VDD_3V66,
VDD_CPU,VDD_RE
F
VDD_48 MHz
VDD_CORE
GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
GND_CPU
GND_CORE
33
22
3, 7, 16, 27, 32,
41
3.3V power supply for 48 MHz.
3.3V power supply for phase-locked loop (PLL).
Ground for outputs.
23
Ground for PLL.
Note:
2. PCI3 is internally disabled and is not accessible.
Document #: 38-07507 Rev. *A
Page 2 of 18
[+] Feedback
CY28339
Two-Wire SMBus Control Interface
The two-wire control interface implements a Read/Write slave
only interface according to SMBus specification.
The device will accept data written to the D2 address and data
may read back from address D3. It will not respond to any
other addresses, and previously set control registers are
retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1. “Command code“ byte
2. “Byte count” byte.
Although the data (bits) in the command is considered “don’t
care,” it must be sent and will be acknowledged. After the
Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Byte 0: CPU Clock Register
[3,4]
Bit
7
6
@Pu
p
0
0
Name
Description
Spread Spectrum Enable.
0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
CPU Clock Power-down Mode Select.
0 = Drive CPUT to 2x IREF and drive CPUC LOW
1 = Tri-state all CPU outputs.
This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#.
3V66_1/VC
H
PCI_STOP#
S2
S1
3V66_1/VCH Frequency Select
0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit.
Reserved
HW
HW
HW
1
Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP#
is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin.
Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only.
Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only.
Reserved
5
4
3
2
1
0
0
Byte 1: CPU Clock Register
Bit
7
6
@Pu
p
1
0
Name
Reserved
CPUT1, CPUC1 CPUT/C Output Functionality Control when CPU_STOP# is asserted.
CPUT2, CPUC2 0 = Drive CPUT to 6x IREF and drive CPUC LOW
1 = three-state all CPU outputs.
This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs
will be three-stated.
CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted.
0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit.
CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted.
0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit.
Reserved
CPUT2, CPUC2 CPUT/C2 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
CPUT1, CPUC1 CPUT/C1 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
Reserved
Description
5
4
3
2
1
0
0
0
0
1
1
1
Notes:
3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.
4. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.
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