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SIT1552AC-J1-AA3-32.768E

产品描述LVCMOS Output Clock Oscillator, 0.032768MHz Nom, CSP, 4 PIN
产品类别无源元件    振荡器   
文件大小855KB,共12页
制造商SiTime
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SIT1552AC-J1-AA3-32.768E概述

LVCMOS Output Clock Oscillator, 0.032768MHz Nom, CSP, 4 PIN

SIT1552AC-J1-AA3-32.768E规格参数

参数名称属性值
厂商名称SiTime
包装说明CSP, 4 PIN
Reach Compliance Codecompliant
其他特性TR
老化1 PPM/FIRST YEAR
最长下降时间200 ns
频率调整-机械NO
频率稳定性20%
安装特点SURFACE MOUNT
标称工作频率0.032768 MHz
最高工作温度70 °C
最低工作温度
振荡器类型LVCMOS
输出负载10 pF
物理尺寸1.54mm x 0.84mm x 0.6mm
最长上升时间200 ns
最大供电电压3.63 V
最小供电电压1.5 V
表面贴装YES
最大对称度52/48 %
Base Number Matches1

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SiT1552
Smallest (1.2 mm
2
), Ultra-Low Power, 32.768 kHz MEMS TCXO
Smallest (1.2mm
2
), Ultra-Low Power, 32.768 kHz MEMS TCXO
Features
Applications
32.768 kHz ±5, ±10, ±20 ppm frequency stability options
over temp
World’s smallest TCXO in a 1.5 x 0.8 mm CSP
Operating temperature ranges:
0°C to +70°C
-40°C to +85°C
Ultra-low power: <1 µA
Vdd supply range: 1.5V to 3.63V
Improved stability reduces system power with fewer
network timekeeping updates
Internal filtering eliminates external Vdd bypass cap and
saves space
Pb-free, RoHS and REACH compliant
Smart Meters (AMR)
Health and Wellness Monitors
Pulse-per-Second (pps) Timekeeping
RTC Reference Clock
Electrical Specifications
Table 1. Electrical Characteristics
Parameter
Symbol
Fout
-5.0
F_stab
-10
-20
F_stab
-10
-13
-22
F_vdd
F_aging
-0.75
-1.5
First Year Frequency Aging
-1.0
Min.
Typ.
32.768
5.0
10
20
10
13
22
0.75
1.5
1.0
ppm
ppm
ppm
ppm
ppm
Max.
Unit
kHz
Stability part number code = E
Stability part number code = F
Stability part number code = 1
Stability part number code = E
Stability part number code = F
Stability part number code = 1
1.8V ±10%
1.5V – 3.63V
T
A
= 25°C, Vdd = 3.3V
Condition
Frequency and Stability
Output Frequency
Frequency Stability Over
Temperature
[1]
(without Initial Offset
[2]
)
Frequency Stability Over
Temperature
(with Initial Offset
[2]
)
Frequency Stability vs Voltage
Jitter Performance (T
A
= over temp)
Long Term Jitter
Period Jitter
35
2.5
µs
pp
ns
RMS
81920 cycles (2.5 sec), 100 samples
Cycles = 10,000, T
A
= 25°C, Vdd = 1.5V – 3.63V
Supply Voltage and Current Consumption
Operating Supply Voltage
Core Supply Current
[3]
Power-Supply Ramp
Vdd
Idd
t_Vdd_
Ramp
180
Start-up Time at Power-up
t_start
1.5
0.99
1.52
100
300
350
380
ms
ms
3.63
V
μA
T
A
= -40°C to +85°C
T
A
= 25°C, Vdd = 1.8V, LVCMOS Output configuration, No Load
T
A
= -40°C to +85°C, Vdd = 1.5V – 3.63V, No Load
Vdd Ramp-Up 0 to 90% Vdd, T
A
= -40°C to +85°C
T
A
= -40°C +60°C, valid output
T
A
= +60°C to +70°C, valid output
T
A
= +70°C to +85°C, valid output
Notes:
1. No board level underfill. Measured as peak-to-peak/2. Inclusive of 3x-reflow and ±20% load variation. Tested with Agilent 53132A frequency counter. Due to
the low operating frequency, the gate time must be ≥100 ms to ensure an accurate frequency measurement.
2. Initial offset is defined as the frequency deviation from the ideal 32.768 kHz at room temperature, post reflow.
3. Core operating current does not include output driver operating current or load current. To derive total operating current (no load), add core operating current
+ output driver operating current, which is a function of the output voltage swing. See the description titled
Calculating Load Current.
Rev 1.4
April 12, 2018
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