Integrated
Circuit
Systems, Inc.
ICS9148-12
Frequency Timing Generator for Pentium/Pro
TM
or Transmeta
TM
Efficeon
TM
General Description
ICS9148-12
is a Clock Synthesizer chip for Pentium/Pro-
based Desktop/Notebook systems or Transmeta Efficeon
Mobile systems.
Features include four strong CPU, seven PCI and eight
SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. Stronger drive CPUCLK
outputs typically provide greater than 1 V/ns slew rate into
20pF loads. This device meets rise and fall requirements
with 2 loads per CPU output (ie, one clock to CPU and NB
chipset, one clock to two L2 cache inputs).
PWR_DWN# pin allows low power mode by stopping
crystal OSC and PLL stages. For optional power
management, CPU_STOP# can stop CPU (0:3) clocks
and PCI_STOP# will stop PCICLK (0:5) clocks. CPU and
IOAPIC output buffer strength controlled by CPU 3.3_2.5#
pin to match VDDL voltage.
PCICLK outputs typically provide better than 1V/ns slew
rate into 30pF loads while maintaining 50±5% duty cycle.
The REF clock outputs typically provide better than 0.5V/
ns slew rates.
The
ICS9148-12
accepts a 14.318MHz reference crystal
or clock as its input and runs on a 3.3V core supply.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU outputs are stronger drive for multiple loads
per pin (ie CPU and NB on one pin)
Generates system clocks for CPU, IOAPIC,
SDRAM, PCI, plus 14.314 MHz REF(0:1), USB,
Plus Super I/O
Supports single or dual processor systems
I
2
C serial configuration interface provides output
clock disabling and other functions
MODE input pin selects optional power
management input control pins
Two fixed outputs separately selectable as 24 or
48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP and 240 mil TSSOP
Output enable register
for serial port control:
1 = enable
0 = disable
Pin Configuration
Block Diagram
48-Pin SSOP & TSSOP
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70
°
C
Crystal (X1, X2) = 14.31818 MHz
SEL
0
0123I—07/18/05
CPUCLK, SDRAM
(MHz)
60
66.6
PCICLK
(MHz)
30
33.3
1
Transmeta and Efficeon are trademarks of Transmeta Corporation.
Pentium/Pro is a trademark of Intel Corporation.
ICS9148-12
Pin Descriptions
PIN NUMBER
2, 1
3, 10, 17, 24,
31, 37, 43
4
5
6
7, 15
8
9, 11, 12, 13, 14, 16
18
19
20
21
22
23
25
26
PIN NAME
REF (0:1)
GND
X1
X2
MODE
VDD2
PCICLK_F
PCICLK (0:5)
SEL66/60#
SDATA
SCLK
VDD4
48/24MHzA
48/24MHzB
VDD
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
VDD3
VDDL2
CPUCLK (0:3)
SDRAM (0:5)
PWR_DWN#
IOAPIC
VDDL1
CPU3.3-2.5#
VDD1
TYPE
OUT
PWR
IN
OUT
IN
PWR
OUT
OUT
IN
IN
IN
PWR
OUT
OUT
PWR
OUT
IN
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
PWR
IN
PWR
DESCRIPTION
Reference clock Output
Ground (common)
Cr ystal or reference input, has internal cr ystal load cap
Cr ystal output, has internal load cap and feedback
resistor to X1
Input function selection
Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
Selects 60MHz or 66.6MHz for SDRAM and CPU
I
2
C data input
I
2
C clock input
Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V
48/24MHz driver output for USB or Super I/O
48/24MHz driver output for USB or Super I/O
Supply for PLL core, nominal 3.3V
SDRAM clock 60/66.6MHz (selected)
Halts PCI Bus (0:5) at logic "0" level when low
SDRAM clock 60/66.6MHz (selected)
Halts CPU clocks at logic "0" level when low
Supply for SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#, nominal 3.3V
Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal
CPUCLK clock output, powered by VDDL2
SDRAMs clock at 60 or 66.6MHz (selected)
Powers down chip, active low
IOAPIC clock output, (14.318MHz) powered by VDDL1
Supply for IOAPIC, either 2.5 or 3.3V nominal
3.3 or 2.5 VDD buffer strength selection, has pullup to
VDD, nominal 30K resistor.
Supply for REF (0:1), X1, X2, nominal 3.3V
27
28, 34
40
42, 41, 39, 38
36, 35, 33, 32, 30, 29
44
45
46
47
48
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#
VDD4 = 48/24MHzA, 48/24MHzB
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
0123I—07/18/05
2
ICS9148-12
Power-On Conditions
SEL 66/60#
MODE
PIN #
38, 39, 41, 42
36, 35, 33, 32,
30, 29, 27, 26
16, 14, 13, 12,
11, 9, 8
38, 39, 41, 42
36, 35, 33, 32,
30, 29, 27, 26
16, 14, 13, 12,
11, 9, 8
26
27
8
1
0
38, 39, 41, 42
36, 35, 33, 32,
30, 29
16, 14, 13, 12,
11, 9
26
27
8
0
0
38, 39, 41, 42
36, 35, 33, 32,
30, 29
16, 14, 13, 12,
11, 9
CPUCLKs
SDRAM
PCICLKs
CPUCLKs
SDRAM
PCICLKs
PCI_STOP#
CPU_STOP#
PCICLK_F
DESCRIPTION
CPUCLKs
SDRAM
PCICLKs
CPUCLKs
SDRAM
PCICLKs
PCI_STOP#
CPU_STOP#
PCICLK_F
FUNCTION
66.6 MHz - w/serial config enable/disable
66.6 MHz - All SDRAM outputs
33.3 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
30 MHz - w/serial config enable/disable
Power Management, PCI (0:5) Clocks
Stopped when low
Power Management, CPU (0:5) Clocks
Stopped when low
33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management
66.6 MHz - CPU Clocks w/exter nal Stop Control
and serial config individual enable/disable.
66.6 MHz - SDRAM Clocks w/serial config
individual enable/disable.
33.3 MHz - PCI Clocks w/exter nal Stop control and
serial config individual enable/disable.
Power Management, PCI (0:5) Clocks
Stopped when low
Power Management, CPU (0:5) Clocks
Stopped when low
30 MHz - PCI Clock Free running for Power
Management
60 MHz - CPU Clocks w/exter nal Stop control and
serial config individual enable/disable.
60 MHz - SDRAM Clocks w/serial config individual
enable/disable.
30 MHz - PCI Clocks w/exter nal Stop control and
serial config individual enable/disable.
1
1
0
1
Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then
produced are on the MODE pin as shown in the table below.
CLOCK
REF (0:1)
I OA P I C 0
48/24 MHz
0123I—07/18/05
D E FAU LT C O N D I T I O N AT P OW E R - U P
14.31818 MHz
14.31818 MHz
48 MHz
3
ICS9148-12
Technical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:1),
PCICLK, 48/24MHzA/B and SDRAM(0:7).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from
Ground to this level. For the actual guaranteed high and
low voltage levels for the Clocks, please consult the DC
parameter table in this data sheet.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI
output buffers. The voltage level for these outputs may
be 2.5 or 3.3volts. Clocks from the buffers that each
supplies will have a voltage swing from Ground to this
level. For the actual Guaranteed high and low voltage
levels of these Clocks, please consult the DC parameter
table in this Data Sheet.
GND
This is the power supply ground (common or negative)
return pin for the internal core logic and all the output
buffers.
X1
This input pin serves one of two functions. When the
device is used with a Crystal, X1 acts as the input pin for
the reference signal that comes from the discrete crystal.
When the device is driven by an external clock signal, X1
is the device input pin for that reference clock. This pin
also implements an internal Crystal loading capacitor
that is connected to ground. See the data tables for the
value of this capacitor.
X2
This Output pin is used only when the device uses a
Crystal as the reference frequency source. In this mode
of operation, X2 is an output signal that drives (or excites)
the discrete Crystal. The X2 pin will also implement an
internal Crystal loading capacitor that is connected to
ground. See the Data Sheet for the value of this
capacitor.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive
processor and other CPU related circuitry that requires
clocks which are in tight skew tolerance with the CPU
clock. The voltage swing of these Clocks are controlled
by the Voltage level applied to the VDDL2 pin of the
device. See the Functionality Table for a list of the
specific frequencies that are available for these Clocks
and the selection codes to produce them.
SDRAM(0:7)
These Output Clocks are use to drive Dynamic RAM’s
and are low skew copies of the CPU Clocks. The voltage
swing of the SDRAM’s output is controlled by the supply
voltage that is applied to VDD3 of the device, operates at
3.3 volts.
48/24MHzA, B
This is a fixed frequency Clock output that is typically
used to drive Super I/O devices. Outputs A and B are
defined as 24 or 48MHz by I
2
C register (see table).
IOAPIC
This Output is a fixed frequency Output Clock that runs
at the Reference Input (typically 14.31818MHz) . Its
voltage level swing is controlled by VDDL1 and may
operate at 2.5 or 3.3volts.
REF(0:1)
The REF Outputs are fixed frequency Clocks that run at
the same frequency as the Input Reference Clock X1 or
the Crystal (typically 14.31818MHz) attached across X1
and X2.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE
RUNNING, and will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing
requirements for a Pentium/Pro based system. They
conform to the current PCI specification. They run at 1/
2 CPU frequency.
SELECT 66.6/60MHz#
This Input pin controls the frequency of the Clocks at the
CPU, PCICLK and SDRAM output pins. If a logic “1” value
is present on this pin, the 66.6 MHz Clock will be
selected. If a logic “0” is used, the 60MHz frequency will
be selected.
0123I—07/18/05
4
ICS9148-12
Technical Pin Function Descriptions
MODE
This Input pin is used to select the Input function of the
I/O pins. An active Low will place the I/O pins in the Input
mode and enable those stop clock functions.
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power
supply requirements for VDDL1,2. A logic “0” (ground) will
indicate 2.5V operation and a logic “1” will indicate 3.3V
operation. This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to
Power Down the device into a Low Power state by not
removing the power supply. The internal Clocks are
disabled and the VCO and Crystal are stopped. Powered
Down will also place all the Outputs in a low state at the
end of their current cycle. The latency of Power Down will
not be greater than 3ms. The I
2
C inputs will be Tri-Stated
and the device will retain all programming information.
This input pin only valid when MODE=0 (Power
Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop
the CPUCLK clocks in an active low state. All other
Clocks including SDRAM clocks will continue to run while
this function is enabled. The CPUCLK’s will have a turn
ON latency of at least 3 CPU clocks. This input pin only
valid when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop
the PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I
2
C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in
the I
2
C protocol. It will allow read-back of the registers.
See configuration map for register functions. The I
2
C
specification in Philips I
2
C Peripherals Data Handbook
(1996) should be followed.
0123I—07/18/05
5
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