MITSUMI
IC for CMOS System Reset PST4XXAXXXN
IC for CMOS System Reset
Monolithic IC PST4XXAXXXN Series
Outline
This is a system reset IC developed using the CMOS process. The CMOS process allows ultra-low current
consumption of 1.5µA(typ.). Further, a fixed delay timer is built in, so that supply voltage is verified when the
power is turned on or interrupted to reset the system accurately.
Features
1. Detection voltage accuracy
±1.5% (25ºC, V
DD
= V
DET
+ 0.1)
2. Low current consumption
SOT-23 : 1.5µA
3. No external capacitor for delay timer required
Built-in delay timer
SOT-23 : 50/100/200/240/400ms
4. Enhanced rank lineup available for detection voltage, package, output configuration and delay timer.
5. Wide operating temperature range
-40 ~ +105ºC.
SOT-23A
Applications
Pin Assignment
Ph
3
1
2
3
as
ed
1. Reset circuits for microcomputers, CPUs and MPUs
2. Reset circuits for logic circuits
3. Battery voltage check circuits
4. Back-up power supply switching circuits
5. Level detection circuits
6. Mechanical reset circuits
1
2
SOT-23A
O
ut
GND
V
OUT
V
DD
Pr
od
Package
uc
ts
MITSUMI
IC for CMOS System Reset PST4XXAXXXN
Absolute Maximum Ratings
Item
Operating Temperature
Storage Temperature
Supply Voltage
Output Voltage
Output Current
Power Dissipation
(Ta=25°C)
Symbol
T
OPR
T
STG
V
DD
max.
V
OUT
I
OUT
P
D
Rating
-40~+105
-65~+160
6.5
GND-0.3~VDD max.+0.3(CMOS Type)
GND-0.3~6.5(N-ch Open Drain Type)
20
150
Unit
°C
°C
V
V
mA
mW
Recommended Operating Conditions
Operating Temperature
T
OPR
-40~+105
Ph
as
ed
O
ut
Pr
od
uc
ts
Item
Symbol
Rating
Unit
°C
MITSUMI
IC for CMOS System Reset PST4XXAXXXN
Electrical Characteristics
Item
V
DD
Range
Detecting Voltage
Detecting Voltage Temp. Coefficient
Supply Current
(Unless otherwise specified, Ta=25°C)
Symbol
V
DD
V
DET
V
DET
/ T
I
SS
PST4
PST4
PST4
V
OH
PST4
PST4
PST4
PST4
Test Conditions
Test Circuit 1
Test Circuit 1
-40˚C<T
OPR
<105˚C Test Circuit1
=
=
V
DD
=V
DET
+0.1 Test Circuit 2
160N ~
230N
240N ~
350N
360N ~
480N
160N ~
350N
480N
360N ~
V
DD
=V
DET
-0.1V
I
OUT
=150µA
V
DD
=V
DET
-0.1V
I
OUT
=500µA
V
DD
=V
DET
-0.1V
I
OUT
=800µA
Min. Typ. Max. Unit
1.0
-1.5%
1.6V~4.8V
(0.1V STEP)
±30
1.5
3.5
6.0
+1.5%
V
V
ppm/˚C
µA
"H" Out put Voltage
(PST41
A /42
A)
0.8V
DD
V
uc
V
DD
=V
DET
+0.1V
I
OUT
=1.2mA
I
OUT
=3.2mA
V
DD
=V
DET
+0.1V
V
DD
=V
DET
+0.1V
I
OUT
=150µA
V
DD
=V
DET
+0.1V
I
OUT
=500µA
V
DD
=V
DET
+0.1V
I
OUT
=800µA
V
DD
=V
DET
-0.1V
I
OUT
=1.2mA
V
DD
=V
DET
-0.1V
I
OUT
=3.2mA
35
70
50
100
200
240
400
20
0.8V
DD
140
170
280
Test Circuit 6
PST4
V
OL
PST4
PST4
PST4
PST4
PST4
PST4
ts
0.3
V
0.4
V
V
0.3
V
0.4
65
130
260
310
520
µs
0.1
µA
ms
V
"L" Out put Voltage
(PST41
A /42
A)
O
PST4
PST4
PST4
PST4
PST4
"H" Out put Voltage
(PST43
A /44
A)
V
OH
ed
V
OL
T
DEL
T
DET
I
LEAK
as
Ph
A /44
A)
A /44
A)
"L" Out put Voltage
(PST43
Reset Active Timeout Period
V
DD
to Reset Delay
Output Leakage Current
(PST42
Note 1: This device is tested at only normal temperature. Over temperature limit guaranteed by desigh only.
Note 2: This device has no Hysteresis Voltage.
ut
PST4
Pr
od
Test Circuit 7
160N ~
230N
350N
360N ~
480N
160N ~
350N
360N ~
480N
240N ~
Test Circuit 6
Test Circuit 7
Test Circuit 8
Test Circuit 8
Test Circuit 5
单片机
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