S i 5 9 0 / 5 91
1 ps M
AX
J
I T T E R
C
RYSTAL
O
SC ILLA TOR
(XO)
(10 M H
Z TO
810 MH
Z
)
Features
Available with any-frequency output
frequencies from 10 to 810 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
Si5602
Applications
Ordering Information:
See page 7.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 supports any
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique
crystal is required for each output frequency, the Si590/591 uses one fixed
crystal to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Si590 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
NC
2
5
NC
V
DD
CLK– CLK+
GND
3
4
CLK
17 k
*
Any-rate
10–810 MHz
DSPLL
®
Clock
Synthesis
Si590 (CMOS)
OE
Fixed
Frequency
XO
OE
1
6
V
DD
NC
2
5
CLK–
17 k
*
GND
3
4
CLK+
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Si591 (LVDS/LVPECL/CML)
Rev. 1.0 8/11
Copyright © 2011 by Silicon Laboratories
Si590/591
Si590/591
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
Tristate mode
Output Enable (OE)
2
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
110
100
90
80
60
—
—
—
Max
3.63
2.75
1.89
125
110
100
90
75
—
0.5
85
Units
V
mA
V
IH
V
IL
T
A
V
ºC
Operating Temperature Range
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2.
OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 7.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2
Initial Accuracy
Symbol
f
O
f
i
Test Condition
LVPECL/LVDS/CML
CMOS
Measured at +25 °C at time of
shipping
Note 3, second option code “D”
Note 3, second option code “C”
Note 4, second option code “B”
Note 4, second option code “A”
second option code “D”
second option code “C”
second option code “B”
second option code “A”
Min
10
10
—
—
—
—
—
—
—
—
—
—
Typ
—
—
±1.5
—
—
—
—
—
—
—
—
—
Max
810
160
—
±20
±30
±50
±100
±7
±20
±25
±50
10
Units
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ms
Total Stability
Temperature Stability
Powerup Time
5
t
OSC
Notes:
1.
See Section 3. "Ordering Information" on page 7 for further details.
2.
Specified at time of order by part number.
3.
Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See
3. "Ordering Information" on page 7.
4.
Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See
3. "Ordering Information" on page 7.
5.
Time from powerup or tristate mode to f
O
.
2
Rev. 1.0
Si590/591
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
V
O
2.5/3.3 V option mid-level
1.8 V option mid-level
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
—
—
1.10
0.35
0.8 x V
DD
V
DD
– 1.30
V
DD
– 0.36
1.50
0.425
—
—
—
2
—
—
—
1.90
0.50
V
DD
V
CML Output Option
2
V
OD
V
PP
V
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
V
OH
V
OL
t
R,
t
F
—
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
—
—
45
0.4
350
—
55
ps
ns
%
SYM
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
3.
C
L
= 15 pF. Sinking or sourcing 12 mA for V
DD
= 3.3 V, 6 mA for V
DD
= 2.5 V, 3 mA for V
DD
= 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1
for 50 MHz < F
OUT
< 810 MHz
(LVPECL/LVDS/CML)
Phase Jitter (RMS)
1
(LVPECL/LVDS/CML)
Phase Jitter (RMS)
2
for 50 MHz < F
OUT
< 160 MHz
(CMOS)
Symbol
Test Condition
12 kHz to 20 MHz
Min
—
Typ
0.5
Max
1.0
Units
ps
J
J
J
12 kHz to 20 MHz,
155.52 MHz output frequency
12 kHz to 20 MHz
—
—
0.4
0.6
0.7
1.0
ps
ps
Notes:
1.
Refer to AN256 for further information.
2.
Single-ended CMOS output phase jitter measured using 33
series termination into 50
phase noise test equipment.
3.3 V supply voltage option only.
Rev. 1.0
3
Si590/591
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
—
—
Max
3
35
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
\
Table 6. Environmental Compliance and Package Information
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
J-STD-020, MSL1
Gold over Nickel
Table 7. Thermal Characteristics
(Typical values T
A
= 25 ºC, V
DD
= 3.3 V)
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Ambient Temperature
Junction Temperature
Symbol
JA
JC
T
A
T
J
Test Condition
Still Air
Still Air
Min
—
—
–40
—
Typ
84.6
38.8
—
—
Max
—
—
85
125
Unit
°C/W
°C/W
°C
°C
4
Rev. 1.0
Si590/591
Table 8. Absolute Maximum Ratings
1
Parameter
Maximum Operating Temperature
Supply Voltage, 1.8 V Option
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
T
AMAX
V
DD
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
85
–0.5 to +1.9
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
2500
260
20–40
Units
ºC
V
V
V
ºC
V
ºC
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.
The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO
for further information, including soldering profiles.
Rev. 1.0
5
FPGA/CPLD
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