Introduction
The Excelitas PGA pulsed laser family
consists of hermetically packaged
devices having up to four active lasing
layers, which are epitaxially grown on a
single GaAs substrate chip. This multi-
layer design multiplies the output power
by the number of epi-layers. For
example, the QPGA quad laser at
225 m active layer width which has four
epitaxially grown lasing layers, delivers an
output peak power >100 W and, by
additionally stacking three quad chips into
a single package, the usable device
power even exceeds 300 W.
The laser chips of the PGA family feature
stripe widths of 75 and 225 m and come
as single (PGA), double (DPGA), triple
(TPGA), or quadruple (QPGA) epi-layer
version, which in addition can be stacked
to increase the output power further.
The PGA series possesses a 25º beam
divergence in the direction perpendicular
to chip surface and a 10° beam spread
within the junction plane. The power
output shows an excellent stability over
the full MIL specification temperature
range. Structures are fabricated using
metal organic chemical vapour deposition
(MOCVD).
Recognizing that different applications
require different packages, six standard
package options are available, including
the traditional stud designs as well as 5.6
and 9 mm CD packages and ceramic
substrates. Since pulse widths in
applications have decreased and optical
coupling has become even more
important, the newer packages -
boasting reduced inductance and thinner,
flatter windows - have gained popularity.
Additionally where fiber coupling
applications are concerned, the
transverse spacing of the EPI cavity
active areas concentrates more optical
power into a smaller geometry allowing
for increased optical power coupling into
optical fibers.
Features and Benefits
•
Doubling, tripling or quadrupling of
the output power from a single
EPI-cavity chip with a small active
area:Peak power exceeds 100 W
at 30 A drive current and 100 ns
pulse width.
•
Peak power >300 W at 30 A drive
current and 100 ns pulse width for
3 physically stacked quad EPI
cavity chips.
•
Extremely high reliability.
The PGA EPI-cavity lasers
family has been proven in safety
applications since early 1990s.
•
Range of single element and
stacked devices.
•
Choice of 6 standard
packages.
•
80% power retention at 85ºC
ambient.
•
Flexibility in customization
for different applications.
•
Small emitting areas allow ease
of fiber coupling.
•
RoHS compliant
Applications
•
Laser range finding.
•
Laser safety curtains
(laser scanning).
•
Infrared night illumination
•
Laser
speed
measurement
(LIDAR).
•
Automotive adaptive cruise control
(ACC).
•
Material excitation in medical
and
other
analytical
applications.
•
Weapon simulation.
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PGA Pulsed Laser Family Selection Table
The following table lists the preferred chip and stacking options. For other configurations please
inquire.
Device
Description
Total # of
emitting
stripes
1
2
3
4
6
Typical peak power at 30 A, 100 ns
75 m (3 mils)
225 m (9 mils)
stripe width
stripe width
8W
15 W
23 W
33 W
45 W
23 W
50 W
75 W
105 W
148 W
PGAx1
DPGAx1
TPGAx1
QPGAx1
TPGAx2
Single chip laser - 1 epi-layer
Single chip laser - 2 epi layers:
Double EPI-cavity laser
Single chip laser - 3 epi-layers:
Triple EPI-cavity laser
Single chip laser - 4 epi-layers:
Quad EPI-cavity laser
Double chip laser - 2 x 3 epi-layers:
Double stacked triple EPI-cavity
laser
Double chip laser - 2 x 4 epi-layers:
Double stacked quad EPI-cavity
laser
Triple chip laser - 3 x 4 epi-layers:
Triple stacked quad EPI-cavity laser
QPGAx2
8
65 W
208 W
QPGAx3
12
95 W
310 W
„x‟ = package type. Preferred package: S-type
Operating Conditions
The laser is operated by pulsing in the forward bias direction.
The Excelitas warranty applies only to devices operated within the maximum rating, as specified.
Exceeding these conditions is likely to cause permanent “burn off” damage to the laser facet and
consequently a significant reduction in optical power.
Operating the devices at increased duty cycles will ultimately and irreparably damage the crystal
structure due to internal heating effects. Diodes are static sensitive and suitable precautions should be
taken when removing the units from their antistatic containers. Circuits should be designed to protect
the diodes from high current and reverse voltage transients. Voltages exceeding the reverse
breakdown of the semiconductor junction are particularly damaging and have been shown to cause
degradation of power output. Although the devices will continue to perform well at elevated
temperatures for some thousands of hours, defect mechanisms are accelerated.
Optimum long term reliability will be attained with the semiconductor at or below room temperature.
Adequate heat sinking should be employed, particularly for the larger stacks and when operated at
maximum duty factor.
Forward Voltage
The forward voltage of the device is a combination of: a static voltage drop resulting from band gaps
and material characteristics, a dynamic series resistance resulting from the contact area dimensions,
the resistivity of the contact layers, and the inductive voltage drop of the package. Voltages due to the
inductive elements are additional and, therefore, are considered separately since they depend on the
package inductance, the pulse rise time and the peak current.
Package Inductance
When narrow pulse widths are required, the system designer must take care that circuit inductance is
kept to a minimum (note inductance on package list). Using the lower inductance packages will
reduce the peak voltage required to obtain the desired drive current.
For example, to obtain approximate Gaussian pulse shapes for the “C” and “U” packages:
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High Power Laser-Diode Family for Industrial Range Finding
2
1. DPGAC1S12H:
t
w
= 40 ns P
rr
= 25 kHz, t
r
= 20 ns, i
r
= 60 A, L
CPKG
= 12 nH
VL = L
PKG
X di/dt
V
CPKG
= 12 x 10
-9
X 60/20 X 10
-9
=36 V
2. DPGAU1S12H:
t
w
= 40 ns P
rr
= 25 kHz, t
r
= 20 ns, i
r
= 60 A, L
CPKG
= 5 nH
VL = L
PKG
X di/dt
V
CPKG
= 5 x 10
-9
X 60/20 X 10
-9
=15 V
Note: These voltage drops are merely to overcome the inductance of the package and do not include
the series package and chip static resistances.
Other circuit elements typically increase voltage requirements to 3 X V
PKG
, therefore the location of
components to minimize lead length is critical.
Maximum Ratings
Parameter
Peak reverse voltage
Pulse duration
Duty factor
Storage temperature
Operating temperature
Soldering for 5 seconds (leads only)
Symbol
V
RM
t
W
du
T
S
T
op
-55
-55
Min
Max
2
100
0.1
105
85
+260
Units
V
ns
%
°C
°C
°C
Generic Electro Optical Specifications at 23°C
Parameter
Center wavelength of spectral envelope
Spectral bandwidth at 50% intensity points
Wavelength temperature coefficient
Beam spread (50% peak intensity)
parallel to junction plane
Beam spread (50% peak intensity)
perpendicular to junction
Symbol
λC
∆λ
∆λ/∆T
ΘH
ΘH
Min
895
Typ
905
5
0.25
10
25
Max
915
Units
nm
nm
nm/°C
degrees
degrees
PGA 75 m Stripe Width Family:
Characteristics at 23°C, 10 A, 100 ns, 0.1% duty cycle
Parameter
Po at i
FM
# of emitting stripes
# of laser chips
Emitting area
Maximum peak
forward current
Threshold current
1
Symbol
min
Po
min
typical Po
typ
PGA
S1S03H
7
8
1
1
75 x 1
10
DPGA
S1S03H
14
15
2
1
75 x 10
10
TPGA
S1S03H
21
23
3
1
75 x 10
10
QPGA
S1S03H
29
33
4
1
75 x 15
10
TPGA
S2S03H
42
45
6
2
75 x
175
10
QPGA
S2S03H
58
65
8
2
75 x
200
10
QPGA
S3S03H
87
95
12
3
75 x
400
10
Units
W
W
typical
i
FM
typical i
th
typical V
f
µm
A
A
V
0.5
1.0
1.0
1.0
1.0
4
7
10
15
18
Forward voltage @ i
FM
Preferred packages
S,Y
S,Y
S,Y
S,Y
S,Y
Optional packages
U,C,F,R U,C,F,R U,C,F,R U,C,F,R U,C,F,R
1) Excluding the voltage drop contribution due to the inductive element of the package.
1.0
1.0
30
45
S,Y
S,Y
U,C,F,R U,C,F,R
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High Power Laser-Diode Family for Industrial Range Finding
3
PGA 225 m Stripe Width Family:
Characteristics at 23°C, 30 A, 100 ns, 0.1% duty cycle
Parameter
Po at i
FM
# of emitting stripes
# of laser chips
Emitting area
Maximum peak
forward current
Threshold current
1
Symbol
min
Po
min
PGA
S1S09H
20
23
1
1
225 x 1
30
1.5
DPGA
S1S09H
46
50
2
1
225 x
10
30
1.5
TPGA
S1S09H
70
75
3
1
225 x
10
30
1.5
QPGA
S1S09H
95
105
4
1
225 x
15
30
1.5
TPGA
S2S09H
140
148
6
2
225 x
175
30
1.5
QPGA
S2S09H
190
205
8
2
225 x
200
30
1.5
QPGA
S3S09H
285
310
12
3
225 x
400
30
1.5
Units
W
W
typical Po
typ
typical
i
FM
typical i
th
typical V
f
µm
A
A
V
Forward voltage @ i
FM
5
8.5
12.6
20
22
40
60
Preferred packages
S,Y
S,Y
S,Y
S,Y
S,Y
S,Y
S,Y
Optional packages
U,C,F,R U,C,F,R U,C,F,R U,C,F,R U,C,F,R U,C,F,R U,C,F,R
1) Excluding the voltage drop contribution due to the inductive element of the package.
Package Drawings
Package S:
Pin out 1. LD Anode
(+), 2. LD Cathode (-)
Case, Inductance 5.2
nH
Package U:
Pin out 1. LD Anode
(+), 2. NC, 3. LD
Cathode (-) Case,
Inductance 5.0 nH
Package C:
Pin out: LD Cathode
(-) Case, Pin LD
Anode (+),
Inductance 12 nH
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High Power Laser-Diode Family for Industrial Range Finding
4
Package R:
Pin out 1. LD Anode
(+), 2. NC, 3. LD
Cathode (-) Case,
Inductance 6.8 nH
Package F:
Pin out: LD Cathode
(-) Case, Pin LD
Anode (+),
Inductance 11 nH
Package Y:
Pin out 1. LD
Cathode (-) chip
bottom, 2. LD Anode
(+) chip top,
Inductance 1.6 nH
Electro-Optical Characteristics
Figure 1
LEFT: Peak Radiant
Intensity vs.
Temperature
RIGHT: Total Peak
Radiant Intensity vs.
Peak Drive Current
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High Power Laser-Diode Family for Industrial Range Finding
5
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