115.2 – 137 MHz, -55 to 125°C, SOT23, Endura™ Series Oscillator
FeaturesFeatures
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Best acceleration sensitivity of 0.1 ppb/g
Any frequencies between 115.2 MHz and 137 MHz accurate
to 6 decimal points
100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±20 ppm
Industry best G-sensitivity of 0.1 PPB/G
LVCMOS/LVTTL compatible output
AEC-Q100 qualified
5-pin SOT23-5 package: 2.9 x 2.8 mm x mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Contact SiTime
for up-screening and LAT programs
Avionics systems
Field communication systems
Telemetry applications
Electrical Characteristics
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
115.20
-20
-25
-30
-50
Operating Temperature
Range (ambient)
T_use
-40
-40
-40
-55
Acceleration (g) sensitivity,
Gamma Vector
Supply Voltage
Current Consumption
F_g
–
Typ.
–
–
–
–
–
–
–
–
–
–
Max.
137
+20
+25
+30
+50
+85
+105
+125
+125
0.1
Unit
MHz
ppm
ppm
ppm
ppm
°C
°C
°C
°C
ppb/g
AEC-Q100 Grade 3
AEC-Q100 Grade 2
AEC-Q100 Grade 1
Extended cold, AEC-Q100 Grade1
Low sensitivity grade; total gamma over 3 axes; 15 Hz to 2 kHz;
MIL-PRF-55310, computed per section 4.8.18.3.1
All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V and
3.3V are supported.
Contact SiTime
for 1.5V support
No load condition, f = 125 MHz, Vdd = 2.25V to 3.63V
No load condition, f = 125 MHz, Vdd = 1.62V to 1.98V
Condition
Refer to Tables 14 to 16 for the exact
list of supported frequencies
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply voltage
and load (15 pF ± 10%).
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Rugged Characteristics
Supply Voltage and Current Consumption
Vdd
Idd
1.62
2.25
–
–
Duty Cycle
Rise/Fall Time
Output High Voltage
DC
Tr, Tf
VOH
45
–
–
90%
1.8
–
6
4.9
–
1.5
1.5
–
1.98
3.63
8
6
55
3
2.5
–
V
V
mA
mA
%
ns
ns
Vdd
Vdd = 2.25V - 3.63V, 20% - 80%
Vdd = 1.8V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Pin 1, OE
Pin 1, OE
Pin 1, OE logic high or logic low
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
VIH
VIL
Z_in
70%
–
–
–
–
100
–
30%
–
Vdd
Vdd
k
Rev. 1.00
July 24, 2020July 24, 2020
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SiT2045B
115.2 – 137 MHz, -55 to 125°C, SOT23, Endura™ Series Oscillator
Table 1. Electrical Characteristics
(continued)
Parameters
Startup Time
Enable/Disable Time
Standby Current
Symbol
T_start
T_oe
I_std
Min.
–
–
–
–
Typ.
–
–
2.6
1.4
0.6
–
–
RMS Phase Jitter (random)
T_phj
–
–
Max.
5.5
130
–
–
–
Unit
ms
ns
A
A
A
Jitter
RMS Period Jitter
T_jitt
1.6
1.8
0.7
1.5
2.5
3
–
–
ps
ps
ps
ps
f = 125 MHz, 2.25V to 3.63V
f = 125 MHz, 1.8V
f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz
Condition
Measured from the time Vdd reaches its rated minimum value
f = 115.20 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Vdd = 2.8V to 3.3V,
ST
= Low, Output is weakly pulled down
Vdd = 2.5V,
ST
= Low, Output is weakly pulled down
Vdd = 1.8V,
ST
= Low, Output is weakly pulled down
Startup and Resume Timing
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output Enable
3
OE/NC
No Connect
4
5
VDD
OUT
Power
Output
Functionality
Electrical ground
[1]
No connect
H
[2]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
Any voltage between 0 and Vdd or Open
[2]
: Specified
frequency output. Pin 3 has no function.
Power supply voltage
[1]
Oscillator output
NC
2
Top View
GND
1
5
OUT
YXXXX
OE/NC
3
4
VDD
Figure 1. Pin Assignments
Notes:
1. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
2. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option.
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance
of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[3]
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Table 4. Thermal Consideration
[4]
Package
SOT23-5
JA, 4 Layer Board
(°C/W)
421
JC, Bottom
(°C/W)
175
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature (ambient)
85°C
105°C
125°C
Maximum Operating Junction Temperature
95°C
115°C
135°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Rev. 1.00
Page 2 of 12
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SiT2045B
115.2 – 137 MHz, -55 to 125°C, SOT23, Endura™ Series Oscillator
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.00
Page 3 of 12
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SiT2045B
115.2 – 137 MHz, -55 to 125°C, SOT23, Endura™ Series Oscillator
Test Circuit and Waveform
Test
Point
Vout
Vdd
tr
5
4
0.1µF
Power
Supply
tf
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
15 pF
(including probe
and fixture
capacitance)
1
2
3
Vdd
1k
OE/ST Function
Figure 2. Test Circuit
[6]
Note:
6. SiT2045 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 3. Waveform
[6]
Timing Diagrams
Vdd
90% Vdd
Vdd
50% Vdd
T_oe
No Glitch
during start up
Pin 4 Voltage
T_start
OE Voltage
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 4. Startup Timing (OE Mode)
[7]
Figure 5. OE Enable Timing (OE Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Disable Timing (OE Mode Only)
Note:
7. SiT2045 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.00
Page 4 of 12
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SiT2045B
115.2 – 137 MHz, -55 to 125°C, SOT23, Endura™ Series Oscillator
FPGA/CPLD
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