AEC-Q100, High Frequency, Single-Chip, One-Output Clock Generator
,
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
AEC-Q100 with extended temperature range (-55°C to 125°C)
Frequencies between 115.2 MHz and 137 MHz accurate to 6 decimal
points
100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±25 ppm
Industry best G-sensitivity of 0.1 PPB/G
LVCMOS/LVTTL compatible output
5-pin SOT23-5 package: 2.9 x 2.8 mm x mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Automotive, extreme temperature and other high-rel electronics
Infotainment systems, collision detection devices, and in-vehicle
networking
Power train control
Electrical Specifications
Table 1. Electrical Characteristics
[1, 2]
Parameters
Output Frequency Range
Symbol
f
Min.
115.20
Typ.
–
Max.
137
Unit
MHz
Condition
Refer to
Table 14 and Table 15
for the exact list of supported
frequencies
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Frequency Range
Frequency Stability and Aging
Frequency Stability
F_stab
-25
-30
-50
Operating Temperature Range
(ambient)
T_use
-40
-40
-55
Supply Voltage
Current Consumption
Vdd
Idd
1.62
2.25
–
–
Duty Cycle
Rise/Fall Time
Output High Voltage
DC
Tr, Tf
VOH
45
–
–
90%
–
–
–
–
–
–
1.8
–
6
4.8
–
1.5
1.5
–
+25
+30
+50
+105
+125
+125
1.98
3.63
8
6
55
3
2.5
–
ppm
ppm
ppm
°C
°C
°C
V
V
mA
mA
%
ns
ns
Vdd
Vdd = 2.25V - 3.63V, 20% - 80%
Vdd = 1.8V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Pin 1, OE
Pin 1, OE
Pin 1, OE logic high or logic low
Measured from the time Vdd reaches its rated minimum value
f = 115.20 MHz. For other frequencies, T_oe = 100 ns + 3 *
cycles
f = 125 MHz, 2.25V to 3.63V
f = 125 MHz, 1.8V
f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz
Operating Temperature Range
Extended Industrial, AEC-Q100 Grade 2
Automotive, AEC-Q100 Grade 1
Extended Temperature, AEC-Q100
All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V
and 3.3V are supported. Contact
SiTime
for 1.5V support
No load condition, f = 125 MHz, Vdd = 2.25V to 3.63V
No load condition, f = 125 MHz, Vdd = 1.62V to 1.98V
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedence
Startup Time
Enable/Disable Time
VIH
VIL
Z_in
T_start
T_oe
70%
–
–
–
–
–
–
100
–
–
–
30%
–
5
130
Jitter
RMS Period Jitter
RMS Phase Jitter (random)
T_jitt
T_phj
–
–
–
–
1.5
1.8
0.7
1.5
2.5
3
–
–
ps
ps
ps
ps
Vdd
Vdd
k
ms
ns
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at
25 °C temperature.
SiTime Corporation
Rev. 1.0
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised May 28, 2015
SiT2025
AEC-Q100, High Frequency, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Table 2. Pin Description
Pin
1
2
3
4
5
Symbol
GND
NC
OE/ NC
VDD
OUT
Power
No Connect
Output
Enable
No Connect
Power
Output
Electrical ground
[4]
No connect
specified frequency output
L: output is high impedance. Only output driver is disabled.
Any voltage between 0 and Vdd or Open : Specified frequency
output. Pin 3 has no function.
Power supply voltage
[4]
Oscillator output
[3]
GND
1
5
Functionality
Top View
OUT
YXXXX
H
[3]
:
NC
2
OE/NC
3
4
VDD
Notes:
3. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option.
4. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Figure 1. Pin Assignments
N
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[5]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
5. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[6]
Package
SOT23-5
JA, 4 Layer Board
(°C/W)
421
JC, Bottom
(°C/W)
175
Note:
6. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[7]
Max Operating Temperature (ambient)
105°C
125°C
Maximum Operating Junction Temperature
115°C
135°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.0
Page 2 of 11
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SiT2025
AEC-Q100, High Frequency, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform
[8]
Test
Point
Vout
Vdd
tr
5
4
0.1µF
Power
Supply
tf
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
15 pF
(including probe
and fixture
capacitance)
1
2
3
1k
Ω
Vdd
OE/ST Function
Figure 2. Test Circuit
Note:
8. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Waveform
Timing Diagrams
u
90% Vdd
Vdd
Vdd
50% Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[9]
OE Voltage
T_oe
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 4. Startup Timing (OE Mode)
Vdd
OE Voltage
50% Vdd
Figure 5. OE Enable Timing (OE Mode Only)
T_oe
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Disable Timing (OE Mode Only)
Note:
9. SiT2025 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.0
Page 3 of 11
www.sitime.com
SiT2025
AEC-Q100, High Frequency, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots
[10]
DUT 1
DUT 6
1.8V
2.5V
2.8V
3.0V
3.3V
DUT 2
DUT 7
DUT 3
DUT 8
DUT 4
DUT 9
DUT 5
DUT 10
25
20
6.5
Frequency (ppm)
-55
-35
-15
5
25
45
65
85
105
125
6.0
5.5
15
)
10
m
p
5
p
(
y
c
0
n
e
u
‐5
q
e
r
F
‐10
Idd (mA)
5.0
4.5
4.0
3.5
3.0
‐15
‐20
‐25
‐55
‐35
‐15
5
25
45
65
85
105
125
Frequency (MHz)
Temperature (°C)
Temperature (°C)
Figure 7. Idd vs Frequency
Figure 8. Frequency vs Temperature
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
4.0
3.5
55
54
53
RMS period jitter (ps)
Duty cycle (%)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
119
121
123
125
127
129
131
133
135
137
52
51
50
49
48
47
46
45
119
121
123
125
127
129
131
133
135
137
Frequency (MHz)
Frequency (MHz)
Figure 9. RMS Period Jitter vs Frequency
Figure 10. Duty Cycle vs Frequency
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
2.5
2.5
2.0
2.0
Rise time (ns)
1.5
Fall time (ns)
-55
-35
-15
5
25
45
65
85
105
125
1.5
1.0
1.0
0.5
0.5
0.0
0.0
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
Temperature (°C)
Figure 11. 20%-80% Rise Time vs Temperature
Figure 12. 20%-80% Fall Time vs Temperature
Rev. 1.0
Page 4 of 11
www.sitime.com
SiT2025
AEC-Q100, High Frequency, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots
[10]
1.8 V
2
1.9
1.8
1.7
)
1.6
s
p
(
1.5
J
P
I
1.4
1.3
1.2
1.1
1
10
30
2.5 V
2.8 V
3.0 V
3.3 V
1
0.9
0.8
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
IPJ (ps)
IPJ (ps)
50
70
90
110
)
0.7
s
p
(
J
P
I
0.6
0.5
0.4
0.3
10
30
50
70
90
110
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Figure 13. RMS Integrated Phase Jitter Random
(12 kHz to 20 MHz) vs Frequency
[11]
Figure 14. RMS Integrated Phase Jitter Random
(900 kHz to 7.5 MHz) vs Frequency
[11]
Notes:
10. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
11. Phase noise plots are measured with Agilent E5052B signal source analyzer.
FPGA/CPLD
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