PF8100; PF8200
Rev. 8.0 — 20 September 2019
12-channel power management integrated circuit for high
performance applications
Product data sheet
1
Overview
The PF8100/PF8200 is a power management integrated circuit (PMIC) designed for
high performance i.MX 8 and S32x based applications. It features seven high efficiency
buck converters and four linear regulators for powering the processor, memory and
miscellaneous peripherals.
Built-in one time programmable memory stores key startup configurations, drastically
reducing external components typically used to set output voltage and sequence of
2
external regulators. Regulator parameters are adjustable through high-speed I C after
start up offering flexibility for different system states.
2
Features
•
•
•
•
•
•
•
•
Up to seven high efficiency buck converters
Four linear regulators with load switch options
RTC supply and coin cell charger
Watchdog timer/monitor
Monitoring circuit to fit ASIL B safety level
One time programmable device configuration
2
3.4 MHz I C communication interface
56-pin 8 x 8 QFN package
NXP Semiconductors
12-channel power management integrated circuit for high performance applications
PF8100; PF8200
3
Simplified application diagram
PF8x00
VSNVS
BUCK1
VIN:
2.7 V to
5.5 V
BUCK2
BUCK3
BUCK4
BUCK5
BUCK6
BUCK7
LDO1
LDO2
LDO3
LDO4
CONTROL
SIGNALS
I
2
C
SIMCARD
SD Card
LPDDR
Memory
DRAM
eMMC Supply
Ethernet
LPDDR_0
Memory
DRAM
SD Card
VDD_SNVS
VDD_MAIN
VDD_MEMC
VIN:
2.7 V to
5.5 V
PF8x00
IMX8QXP
VSNVS
BUCK1
VDD_MAIN
BUCK2
BUCK3
BUCK4
BUCK5
BUCK6
BUCK7
LDO1
LDO2
LDO3
LDO4
CONTROL
SIGNALS
I
2
C
CPU1
(A72)
GPU0
VDD_SNVS
PF8x00
IMX8QM
VSNVS
BUCK1
BUCK2
BUCK3
GPU1
BUCK4
VDD_MEMC
VDD_DDRIO1
3.3 V I/O
VDD_SIM
SDCARD1
2.5 V I/O
MISC
BUCK5
BUCK6
BUCK7
LDO1
LDO2
LDO3
LDO4
CONTROL
SIGNALS
I
2
C
SD Card
VIN:
2.7 V to
5.5 V
VDD_GPU
VDD_CPU (A35)
VDD_DDRIO
1.8 V I/O
(LV GPIO)
3.3 V I/O
(HV GPIO)
VDD_SCU
SDCARD0
2.5 V I/O
MISC
INTERFACING AND
I
2
C COMMUNICATIONS
CPU0 (A53)
VDD_DDRIO0
1.8 V I/O
VDD_SCU
SDCARD0
3.3 V I/O
MISC
INTERFACING AND
I
2
C COMMUNICATIONS
SIMCARD
Ethernet
eMMC Supply
MISCELLANEOUS
PERIPHERALS
MISCELLANEOUS
PERIPHERALS
DRAM
LPDDR_1
Memory
aaa-028047
Figure 1. Simplified application diagram
4
Type
Ordering information
Package
Name
Description
HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package,
wettable flanks; 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body
HVQFN56, plastic, thermally enhanced very thin quad; flat non-leaded package,
56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.85 mm body
Version
SOT684-21
(DD/SC)
SOT684-21
Table 1. Device options
PF8100 (automotive)
PF8200 (automotive)
PF8100 (industrial)
HVQFN56
Table 2. Ordering information
Part number
[1]
Target market
Automotive
[2]
NXP processor
n/a
i.MX8QXP
i.MX8QXP
i.MX8QM
LS1046A
i.MX8QM
i.MX8QM
i.MX8QM
i.MX8QXP
LA1575
n/a
i.MX8QXP
System comments
Not programmed
LPDDR4 memory
DDR3L memory
DDR4 memory PMIC2
DDR4 Memory (VDDQ +
VTT)
LPDDR4 memory PMIC1
LPDDR4 memory PMIC2
DDR4 memory PMIC1
LPDDR4 memory
LDDR4 memory
Not programmed
LPDDR4 memory
Safety grade
QM
QM
QM
QM
QM
QM
QM
QM
QM
QM
QM
QM
OTP ID
n/a
http://www.nxp.com/MC33PF8100CCES-OTP-Report
http://www.nxp.com/MC33PF8100CFES-OTP-Report
http://www.nxp.com/MC33PF8100CHES-OTP-Report
http://www.nxp.com/MC33PF8100EAES-OTP-Report
http://www.nxp.com/MC33PF8100EPES-OTP-Report
http://www.nxp.com/MC33PF8100EQES-OTP-Report
http://www.nxp.com/MC33PF8100ERES-OTP-Report
http://www.nxp.com/MC33PF8100FJES-OTP-Report
http://www.nxp.com/MC33PF8100F3ES-OTP-Report
n/a
http://www.nxp.com/MC34PF8100CCEP-OTP-Report
MC33PF8100A0ES
MC33PF8100CCES
MC33PF8100CFES
MC33PF8100CHES
MC33PF8100EAES
MC33PF8100EPES
MC33PF8100EQES
MC33PF8100ERES
MC33PF8100FJES
MC33PF8100F3ES
MC34PF8100A0EP
MC34PF8100CCEP
[2]
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Industrial
Industrial
PF8100_PF8200
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 8.0 — 20 September 2019
2 / 131
NXP Semiconductors
12-channel power management integrated circuit for high performance applications
Part number
[1]
PF8100; PF8200
Target market
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
Automotive
NXP processor
i.MX8QXP
i.MX8QM
i.MX8QM
i.MX8QM
i.MX8QM
i.MX8QXP
LA1575
n/a
LS1043A
S32V234
i.MX8QM
i.MX8QXP
i.MX8QXP
i.MX8QM
LS1043
i.MX8QM
i.MX8QM
System comments
DDR3L memory
DDR4 memory PMIC2
LPDDR4 memory PMIC1
LPDDR4 memory PMIC2
DDR4 memory PMIC1
LPDDR4 memory
LDDR4 memory
Not programmed
LPDDR4 memory
DDR3L memory 10 A core
LPDDR4 memory PMIC2
LPDDR4 memory
DDR3L memory
DDR4 memory PMIC2
Triple phase (VDD)
LPDDR4 memory PMIC1
DDR4 memory PMIC1
Safety grade
QM
QM
QM
QM
QM
QM
QM
ASIL B
ASIL B
ASIL B
ASIL B
ASIL B
ASIL B
ASIL B
ASIL B
ASIL B
ASIL B
OTP ID
http://www.nxp.com/MC34PF8100CFEP-OTP-Report
http://www.nxp.com/MC34PF8100CHEP-OTP-Report
http://www.nxp.com/MC34PF8100EPEP-OTP-Report
http://www.nxp.com/MC34PF8100EQEP-OTP-Report
http://www.nxp.com/MC34PF8100EREP-OTP-Report
http://www.nxp.com/MC34PF8100FJEP-OTP-Report
http://www.nxp.com/MC34PF8100F3EP-OTP-Report
n/a
http://www.nxp.com/MC33PF8200CXES-OTP-Report
http://www.nxp.com/MC33PF8200D2ES-OTP-Report
http://www.nxp.com/MC33PF8200DBES-OTP-Report
http://www.nxp.com/MC33PF8200DEES-OTP-Report
http://www.nxp.com/MC33PF8200DFES-OTP-Report
http://www.nxp.com/MC33PF8200DHES-OTP-Report
http://www.nxp.com/MC33PF8200EMES-OTP-Report
http://www.nxp.com/MC33PF8200ESES-OTP-Report
http://www.nxp.com/MC33PF8200ETES-OTP-Report
MC34PF8100CFEP
MC34PF8100CHEP
MC34PF8100EPEP
MC34PF8100EQEP
MC34PF8100EREP
MC34PF8100FJEP
MC34PF8100F3EP
MC33PF8200A0ES
MC33PF8200CXES
MC33PF8200D2ES
MC33PF8200DBES
MC33PF8200DEES
MC33PF8200DFES
MC33PF8200DHES
MC33PF8200EMES
MC33PF8200ESES
MC33PF8200ETES
[1]
[2]
To order parts in tape and reel, add the R2 suffix to the part number.
Not recommended for new designs
5
Applications
•
Automotive Infotainment
•
High-end consumer and industrial
PF8100_PF8200
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 8.0 — 20 September 2019
3 / 131
NXP Semiconductors
12-channel power management integrated circuit for high performance applications
PF8100; PF8200
6
Internal block diagram
VDDIO
SCL
SDA
VDDOTP
RESETBMCU
WDI
PWRON
STANDBY
TBBEN
XINT
INTB
EWARNB
PGOOD
FSOB
FAIL SAFE
CONTROL
SW1FB
SW1
VMON
REF
SELEC.
V
BG2
MONITORING
BANDGAP
WATCHDOG
TIMER
V
BG2
XFAILB
SW1IN
BANDGAP
COMPARATOR
V
BG1
SW1LX
EA
AND
DRIVER
EPAD
SW1 DVS
AND MISC
REFERENCE
WD monitoring
REGULATION
BANDGAP
SW2FB
SW2
VMON
REF
SELEC.
V
BG2
DIGITAL CORE
AND
STATE MACHINE
V1P5A
LDO
V1P5D
LDO
V1P5A
V1P5D
SW2IN
OTP MEMORY
COIN CELL
CHARGER
LICELL
VSNVS
VSNVS
SW2LX
EA
AND
DRIVER
EPAD
SW2 DVS
AND MISC
REFERENCE
THERMAL MONITORING
/ SHUTDOWN
SW3FB
SW3
VMON
REF
SELEC.
V
BG2
SW1VMON
SW2VMON
SW3VMON
SW4VMON
SW5VMON
SW6VMON
SW7VMON
LDO1VMON
LDO2VMON
LDO3VMON
LDO4VMON
PGOOD
MONITORS
PMIC
INTERNAL
MONITORS
10 x DIE
TEMPERATURE
MONITORS
24 CHANNEL
ANALOG MUX
EXTERNAL
CHANNEL
INPUT
VIN
OVLO
VIN
DGND
AGND
AMUX
SW3IN
SW3LX
EA
AND
DRIVER
EPAD
SW3 DVS
AND MISC
REFERENCE
SW4FB
SW4
VMON
REF
SELEC.
CLOCK MANAGEMENT
(100 kHz / 20 MHz / PLL /
DIGITAL MODULE)
MANUAL TUNING
SPREAD SPECTRUM
EXTERNAL CLOCK
SYNC
SYNCOUT
SYNCIN
V
BG2
LDO1 VMON
LDO1OUT
LDO1
LDO12IN
LDO2
SW4IN
V
BG2
EA
AND
DRIVER
EPAD
SW4 DVS
AND MISC
REFERENCE
SW6 DVS
AND MISC
REFERENCE
÷2
REF
SELEC.
V
BG2
VTT
REFERENCE
SELECTOR
V
BG2
LDO2OUT
SW4LX
LDO2 VMON
VSELECT
LDO2EN
SW5FB
SW5
VMON
REF
SELEC.
SW6
VMON
SW7
VMON
V
BG2
SW7 MISC
REFERENCE
V
BG2
LDO3 VMON
LDO30UT
LDO3
LDO3IN
LDO4IN
LDO4
LDO4OUT
SW5IN
EA
AND
DRIVER
EPAD
V
BG2
SW5 DVS
AND MISC
REFERENCE
EA
AND
DRIVER
EPAD
EA
AND
DRIVER
EPAD
V
BG2
LDO4 VMON
SW5LX
SW6FB
SW6IN
SW6LX
SW7FB
SW7IN
SW7LX
Digital Signal(s)
Analog Reference(s)
20 MHz Clock/Derivative
100 kHz Clock/Derivative
aaa-028048
Figure 2. Internal block diagram
PF8100_PF8200
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 8.0 — 20 September 2019
4 / 131
NXP Semiconductors
12-channel power management integrated circuit for high performance applications
PF8100; PF8200
7
Pinning information
7.1 Pinning
49
SYNCOUT
53
VDDOTP
43 LDO2EN
42 PGOOD
41 V1P5A
40 V1P5D
39 XINTB
38
SW7FB
37
SW7IN
EPAD
36
SW7LX
35
SW6IN
34
SW6LX
33
SW5LX
32
SW5IN
31
SW5FB
30
SW6FB
29 FSOB
LDO1OUT
15
VSELECT
16
LDO12IN
17
LDO2OUT
18
WDI 19
EWARN 20
RESETBMCU 21
PWRON 22
STANDBY 23
INTB 24
LDO3OUT
25
LDO3IN
26
LDO4IN
27
LDO4OUT
28
48
SYNCIN
44 XFAILB
47
VSNVS
46
LICELL
54
VDDIO
45 DGND
51
AGND
52 AMUX
56 SDA
55 SCL
DNC1
SW2FB
SW1FB
SW1IN
SW1LX
SW2LX
SW2IN
SW3IN
SW3LX
1
2
3
4
5
6
7
8
9
SW4LX
10
SW4IN
11
SW4FB
12
SW3FB
13
TBBEN 14
50
VIN
aaa-028049
Figure 3. Pin configuration for HVQFN56
7.2 Pin description
Table 3. HVQFN56 pin description
Pin number
1
2
3
4
5
6
7
8
9
10
11
PF8100_PF8200
Symbol
DNC1
SW2FB
SW1FB
SW1IN
SW1LX
SW2LX
SW2IN
SW3IN
SW3LX
SW4LX
SW4IN
Application description
Do not connect
Buck 2 output voltage feedback
Buck 1 output voltage feedback
Buck 1 input supply
Buck 1 switching node
Buck 2 switching node
Buck 2 input supply
Buck 3 input supply
Buck 3 switching node
Buck 4 switching node
Buck 4 input supply
Pin type
—
I
I
I
O
O
I
I
O
O
I
Min
—
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
Max
—
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
Units
V
V
V
V
V
V
V
V
V
V
V
© NXP B.V. 2019. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 8.0 — 20 September 2019
5 / 131
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