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• Organization: 256K×8 or 128K×16
• Sector architecture
- One 16K; two 8K; one 32K; and three 64K byte sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 5.0±0.5V power supply for read/write operations
• Sector protection
• High speed 55/70/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified ad-
dress
• Automated on-chip erase algorith
- Automatically preprograms/erases chip or specified sec-
tors
• 10,000 write/erase cycle endurance
• Hardware RESET pin
- Resets internal state machine to read mode
• Low power consumption
- 20 mA typical read current
- 30 mA typical program current
- 300 µA typical standby current
- 1 µA typical standby current (RESET = 0)
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- RY/BY output
• Erase suspend/resume
- Supports reading data from a sector not being erased
• Low V
CC
write lock-out below 2.8V
/RJLF#EORFN#GLDJUDP
RY/BY
V
CC
V
SS
RESET
Program/erase
control
Command
register
CE
OE
A-1
Program voltage
generator
Chip enable
Output enable
Logic
STB
Data latch
Sector protect
switches
Erase voltage
generator
DQ0–DQ15
3LQ#DUUDQJHPHQW
48-pin TSOP
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1
NC
RY/BY
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
44-pin SO
Input/output
buffers
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AS29F200
AS29F200
WE
BYTE
)/$6+
)/$6+
)/$6+
)/$6+
V
CC
detector
Timer
Address latch
STB
Y decoder
Y gating
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
X decoder
Cell matrix
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V
SS
CE
A0
A0–A16
6HOHFWLRQ#JXLGH
29F200-55
Maximum access time
Maximum chip enable access time
Maximum output enable access time
t
AA
t
CE
t
OE
55
55
25
29F200-70
70
70
30
29F200-90
90
90
35
29F200-120 Unit
120
120
50
ns
ns
ns
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Copyright ©1998 Alliance Semiconductor. All rights reserved.
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The AS29F200 is a 2 megabit, 5 volt only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. For flexible
erase and program capability, the 2 megabits of data is divided into 7 sectors: one 16K byte, two 8K byte, one 32K byte, and three 64K bytes.
The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29F200 is offered in JEDEC standard 44-pin SO and 48-pin
TSOP packages. This device is designed to be programmed and erased in-system with a single 5.0V V
CC
supply. The device can also be
reprogrammed in standard EPROM programmers.
The AS29F200 offers access times of 55/70/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus
contention the device has separate chip enable (CE), write enable ( WE), and output enable ( OE) controls. Word mode (×16 output) is
selected by BYTE = High.
The AS29F200 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register using
standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device in the same
manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm
that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated
on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase
pulse widths, and verifies proper cell margin.
Boot sector architecture enables the device to boot from either the top (AS29F200T) or bottom (AS29F200B) sector. Sector erase architecture
allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically eras es and
verifies within 1.6 seconds. Hardware sector protection disables both program and erase operations in all or any combination of the seven
sectors. The device provides background erase with Erase Suspend, which puts erase operations on hold to read data from a sector that is not
being erased. The chip erase command will automatically erase all unprotected sectors.
A factory shipped AS29F200 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one
byte/word at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes/
words in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.
The device features single 5.0V power supply operation for both read and write functions. Internally generated and regulated voltages are
provided for the program and erase operations. A low V
CC
detector automatically inhibits write operations during power transtitions. The
RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically
resets to the read mode after program/erase operations are completed.
The AS29F200 resists accidental erasure or spurious programming signals resulting from power transitions. Control register archi tecture
permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set
to read mode with all program/erase commands disabled when V
CC
is less than V
LKO
(lockout voltage). The command registers are not
affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands.
)/$6+
When the device’s hardware RESET pin is driven low, any program/erase operation in progress will be terminated and the internal state
machine will be reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-
chip program/erase algorithm, data in address locations being operated on will become corrupted and require rewriting. Resetting the
device enables the system’s microprocessor to read boot-up firmware from the Flash memory.
The AS29F200 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes/words are programmed
one at a time using EPROM programming mechanism of hot electron injection.
5
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Bottom boot sector architecture (AS29F200B)
Sector
0
1
2
3
4
5
6
×8
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
×16
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
Size
(Kbytes)
16
8
8
32
64
64
64
Top boot sector architecture (AS29F200T)
×8
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–37FFFh
38000h–39FFFh
3A000h–3BFFFh
3C000h–3FFFFh
×16
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1BFFFh
1C000h–1CFFFh
1D000h–1DFFFh
1E000h–1FFFFh
Size
(Kbytes)
64
64
64
32
8
8
16
In word mode, there are one 8K word, two 4K word, one 16K word, and three 32K word sectors. Address range is A16–A-1 if BYTE = V
IL
; address range is
A16–A0 if BYTE = V
IH
.
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Bottom boot sector address (AS29F200B)
Sector
0
1
2
3
4
5
6
A16
0
0
0
0
0
1
1
A15
0
0
0
0
1
0
1
A14
0
0
0
1
X
X
X
A13
0
1
1
X
X
X
X
A12
X
0
1
X
X
X
X
A16
0
0
1
1
1
1
1
Top boot sector address (AS29F200T)
A15
0
1
0
1
1
1
1
A14
X
X
X
0
1
1
1
A13
X
X
X
X
0
0
1
A12
X
X
X
X
0
1
X
2SHUDWLQJ#PRGHV
Mode
ID read MFR code
ID read device code
Read
Standby
Output disable
Write
Enable sector protect
Sector unprotect
Verify sector protect
Temporary sector
unprotect
Hardware Reset
CE
L
L
L
H
L
L
L
L
L
X
X
OE
L
L
L
X
H
H
V
ID
V
ID
L
X
X
WE
H
H
H
X
H
L
Pulse/L
Pulse/L
H
X
X
A0
L
H
A0
X
X
A0
L
L
L
X
X
A1
L
L
A1
X
X
A1
H
H
H
X
X
A6
L
L
A6
X
X
A6
L
H
L
X
X
A9
V
ID
V
ID
A9
X
X
A9
V
ID
V
ID
V
ID
X
X
RESET
H
H
H
H
H
H
H
H
H
V
ID
L
DQ
Code
Code
D
OUT
High Z
High Z
D
IN
X
X
Code
X
High Z
)/$6+
)/$6+
)/$6+
)/$6+
L = Low (<V
IL
); H = High (>V
IH
); V
ID
= 12.0 ± 0.5V; X = don’t care; In ×16 mode, BYTE = V
IH
. In ×8 mode, BYTE = V
IL
and DQ8–14 is High Z with
DQ15 = A-1(X).
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Item
ID MFR code,
device code
Read mode
Standby
Description
Selected by A9 = V
ID
(11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs.
When A0 is low (V
IL
) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
When A0 is high (V
IH
), D
OUT
represents the device code for the AS29F200.
Selected with CE = OE = L, WE = H. Data is valid in t
ACC
time after addresses are stable, t
CE
after CE is low
and t
OE
after OE is low.
Selected with CE = H. Part is powered down, and I
CC
reduced to <2.0 mA for TTL input levels. If activated
during an automated on-chip algorithm, the device completes the operation before entering standby.
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors.
Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection.
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A12–16 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
Temporarily disables sector protection for in-system data changes to protected sectors. Apply +12V to RESET
to activate sector unprotect mode. During temporary sector unprotect mode, program protected sectors by
selecting the appropriate sector address. All protected sectors revert to protected state on removal of +12V
from RESET.
Resets the write and erase state machine to read mode. If device is programming or erasing when
RESET = L, data may be corrupted.
Hold RESET low to enter deep power down mode (
<
10 µA CMOS). Recovery time to active mode is 1.5 µs.
Output disable Part remains powered up; but outputs disabled with OE pulled high.
Write
Enable
sector protect
Sector
unprotect
Verify
sector protect
Temporary
sector
unprotect
RESET
)/$6+
Deep
power down
5($'#FRGHV
Mode
MFR code (Alliance Semiconductor)
×8 T boot
Device code
×8 B boot
×16 T boot
×16 B boot
Sector protection
Key: L =Low (<V
IL
); H = High (>V
IH
); X =Don’t care; T = top; B = botto
A16–A12
X
X
X
X
X
Sector address
A6
L
L
L
L
L
L
A1
L
L
L
L
L
H
A0
L
H
H
H
H
L
Code
52h
51h
57h
2251h
2257h
01h protected
00h unprotected
7
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Status
Auto programming (byte/word)
Program/erase in auto erase
Read erasing sector
In progress
Erase
suspend
mode
Read non-erasing
sector
Program in erase
suspend
DQ7
DQ7
0
1
Data
DQ7
DQ7
0
DQ7
DQ6
Toggle
Toggle
No toggle
Data
Toggle
Toggle
Toggle
Toggle
DQ5
0
0
0
Data
0
1
1
1
DQ3
0
1
0
Data
0
NA
1
NA
DQ2
No toggle
Toggle
†
Toggle
Data
Toggle
†
No toggle
Toggle
‡
RY/BY
0
0
1
1
0
1
1
Auto programming (byte/word)
Exceeded time limits
Program/erase in auto erase
Program in erase suspend
No toggle
‡
1
†Toggles with OE or CE only for erasing or erase suspended sector addresses.
‡Toggles only if DQ5 = 1 and address applied is within sector that exceeded timing limits.
DQ8–DQ15 = Don’t care in ×16 mode.
&RPPDQG#GHILQLWLRQV
Item
Description
Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.
Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.
AS29F200 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +12V on A9. AS29F200 also contains an ID read
command to read the device code with only +5V, since multiplexing +12V on address lines is
generally undesirable.
Reset/Read
)/$6+
)/$6+
)/$6+
)/$6+
ID Read
Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XX00h to return MFG code. Follow ID read command
sequence with a read sequence from address XX01h to return device code.
To verify write protect status on sectors, read address XX02h. Sector addresses A16–A12 produce a
1 on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read/Reset command sequence.
Holding RESET low for 500 ns resets the device, terminating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven
low. RY/BY remains low until the RESET operation is completed. After RESET is set high, there is a
delay of 1.5 µs for the device to permit read operations.
Hardware Reset
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