VX-705
Voltage Controlled Crystal Oscillator
VX-705
Description
The VX-705 is a Voltage Control Crystal Oscillator that operates at the fundamental frequency of the internal crystal. The crystal is a high-Q
quartz device that enables the circuit to achieve low phase noise jitter performance over a wide operating temperature range. The VX-705 is
housed in an industry standard hermetically sealed LCC package and is available in tape and reel.
Features
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CMOS or LVPECL output VCXO
Output Frequencies from 77.76 MHz to 204.800 MHz
3.3 V Operation
Fundamental Crystal Design with Low Jitter Performance
Output Disable Feature
Excellent ±20 ppm Temperature Stability,
0/70°C, -20/70°C or -40/85°C Operating Temperature
Small Industry Standard Package, 5.0x7.0
Product is free of lead and compliant to EC RoHS Directive
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LTE
Applications
SONET/SDH/DWDM
Ethernet, SyncE, GE
xDSL, PCMIA
Digital Video
Broadband Access
Base Stations, Picocells
Test and Measurement
Block Diagram
V
DD
NC
Output
Crystal
Oscillator
V
C
E/D
Gnd
Figure 1. Block Diagram
Page1
Table 1. Electrical Performance - 3.3V CMOS
Parameter
Voltage
1
Current
2
Nominal Frequency
3
Absolute Pull Range
2,6
,
ordering option
Linearity
2
Gain Transfer
2
Temperature Stability
Output Logic Levels
2
Output Logic High
Output Logic Low
Load
Rise Time
2,4
Fall Time
2,4
Symmetry
2
Jitter, RMS
5,7
(12kHz to 20 MHz)
Phase Noise
8
(122.88 MHz)
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Performance Specifications
Performance Specifications
Symbol
V
DD
I
DD
Frequency
f
N
APR
Lin
K
V
f
STAB
Outputs
V
V
OH
V
OL
I
OUT
t
R
t
F
SYM
фJ
45
50
80
-66
-98
-124
-138
-151
-158
-161
Control Voltage
V
C
Z
IN
BW
V
IH
V
IL
T
S
T
OP
0/70, -20/70 or -40/85
5.0 x 7.0 x 1.8
0.3
1
10
0.9*V
DD
0.1*V
DD
10
ms
°C
mm
3.0
V
MΩ
kHz
V
0.9*V
DD
0.1*V
DD
15
5
5
55
200
pF
ns
ns
%
fsec
dBc/Hz
80.00
±30 or ±50
5
+80
±20
170.00
MHz
ppm
%
ppm/V
ppm
Min
Supply
3.135
Typical
3.3
10
Maximum
3.465
25
Units
V
mA
Control Voltage Range for Pull Range
Control Voltage Input Impedance
Control Voltage Modulation BW
Output Enable/Disable
9
Output Enabled
Output Disabled
Start-Up Time
Operating Temp, Ordering Option
Package Size
1]
2]
3]
4]
5]
6]
7]
8]
9]
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for examples 0.1 and 0.01uF
Parameters are tested with production test circuit as shown in Figure 2.
See Standard Frequencies and Ordering Information tables for more specific information
Measured from 20% to 80% of a full output swing as shown in Figure 4.
Not tested in production, guaranteed by design, verified at qualification.
Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description
Broadband Period Jitter measured using Wavecrest SIA3300C, 90K samples.
Phase Noise is measured with an Agilent E5052A.
The Output is Enabled if the Enable/Disable is left open.
Page2
Performance Specifications
Table 2. Electrical Performance - 3.3V LVPECL
Parameter
Voltage
1
Current
2
Nominal Frequency
3
Absolute Pull Range
2,6
,
ordering option
Linearity
2
Gain Transfer
2
Temperature Stability
Output Logic Levels
2
Output Logic High
Output Logic Low
Rise Time
2,4
Fall Time
2,4
Symmetry
2
Jitter, RMS
5,8
(12kHz to 20 MHz)
Jitter, RMS
5,8
(10kHz to 1MHz)
Phase Noise
8
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Control Voltage
Control Voltage Range for Pull Range
Control Voltage Input Impedance
Control Voltage Modulation BW
Output Enable/Disable
9
Output Enabled, Option A
Output Disabled, Option A
Start-Up Time
Operating Temp, Ordering Option
Package Size
1]
2]
3]
4]
5]
6]
7]
8]
9]
Symbol
V
DD
I
DD
Min
Supply
3.135
Frequency
Typical
3.3
50
Maximum
3.465
90
204.800
Units
V
mA
MHz
ppm
%
ppm/V
ppm
V
f
N
APR
Lin
K
V
f
STAB
77.76
±30, ±50
5
+80
±20
Outputs
V
OH
V
OL
t
R
t
F
SYM
фJ
фJ
V
DD
-1.025
V
DD
-1.810
V
DD
-0.950
V
DD
-1.700
0.6
0.6
V
DD
-0.880
V
DD
-1.620
1
1
55
1
0.3
ns
ns
%
ps
ps
dBc/Hz
45
50
0.3
0.2
-60
-88
-118
-131
-145
-153
-156
V
C
Z
IN
BW
V
IH
V
IL
T
S
T
OP
0.3
1
10
0.9*V
DD
3.0
V
MΩ
kHz
V
0.1*V
DD
10
0/70, -20/70, or -40/85
5.0 x 7.0 x 1.8
ms
°C
mm
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for examples 0.1 and 0.01uF
Parameters are tested with production test circuit below as shown in Figure 3.
See Standard Frequencies and Ordering Information tables for more specific information
Measured from 20% to 80% of a full output swing as shown in Figure 4.
Not tested in production, guaranteed by design, verified at qualification.
Tested with Vc = 0V to 3.3V unless otherwise stated in part description
Broadband Period Jitter measured using Wavecrest SIA3300C, 90K samples.
Phase Noise is measured with an Agilent E5052A.
The Output is Enabled if the Enable/Disable is left open.
Page3
Test Circuits
I
DD
6
+
V
DD
-
.1µF
.01µF
I
C
V
C
1
+
-
4
3
15pF
Figure 2. CMOS Test Circuit
Figure 3. LVPECL Test Circuit
Waveform
t
R
0.8*VDD
50%
0.2*VDD
On Time
t
F
Period
Figure 4. Output Waveform
Table 3. Absolute Maximum Ratings
Parameter
Power Supply
Voltage Control Range
Storage Temperature
Soldering Temp/Time
Symbol
V
DD
V
C
TS
T
LS
Ratings
0 to 6
0 to V
CC
-55 to 125
260 / 20
Unit
V
V
°C
°C / sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or
any other conditions in excess of conditions represented in the operational sections of this datasheet. Exposure to absolute maximum
ratings for extended periods may adversely affect device reliability. Permanent damage is also possible if OD or Vc is applied before Vcc.
Page4
Phase Noise
Gain
Figure 5A. Typical Phase Noise - 122.88 MHz CMOS
Figure 5B. Typical Gain - 122.88 MHz CMOS
Figure 6A. Typical Phase Noise - 125.00 MHz PECL
Figure 6B. Typical Gain - 125.00 MHz PECL
Page5
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