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MO9120DA6-B0K-33S0-0212500000Y

产品描述LVPECL Output Clock Oscillator, 212.5MHz Nom,
产品类别无源元件    振荡器   
文件大小586KB,共8页
制造商KDS大真空
官网地址http://www.kds.info/
标准
下载文档 详细参数 全文预览

MO9120DA6-B0K-33S0-0212500000Y概述

LVPECL Output Clock Oscillator, 212.5MHz Nom,

MO9120DA6-B0K-33S0-0212500000Y规格参数

参数名称属性值
是否Rohs认证符合
Objectid7213004713
Reach Compliance Codeunknown
其他特性STANDBY; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR
最长下降时间0.5 ns
频率调整-机械NO
频率稳定性50%
安装特点SURFACE MOUNT
标称工作频率212.5 MHz
最高工作温度70 °C
最低工作温度-20 °C
振荡器类型LVPECL
输出负载50 OHM
物理尺寸7.0mm x 5.0mm x 0.9mm
最长上升时间0.5 ns
最大供电电压3.63 V
最小供电电压2.97 V
标称供电电压3.3 V
表面贴装YES
最大对称度55/45 %

文档预览

下载PDF文档
MO9120
Standard Frequency Differential Oscillator
Features
Applications
31 standard frequencies from 25 MHz to 212.5 MHz
LVPECL and LVDS output signaling types
0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±10 ppm
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2x2.5, 5.0x3.2 and 7.0x5.0 mmxmm
For any other frequencies between 1 to 625 MHz, refer to MO9121
and MO9122 datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Telecom, networking, instrumentation, storage, servers
Electrical Characteristics
Parameter and Conditions
Symbol
Min.
Typ.
Max.
Unit
Condition
LVPECL and LVDS, Common Electrical Characteristics
+2.97
Supply Voltage
Output Frequency Range
Vdd
f
+2.25
+2.25
25
-10
Frequency Stability
F_stab
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Z_in
Start-up Time
Resume Time
Duty Cycle
T_start
T_resume
DC
F_aging1
F_aging10
T_use
-2.0
-5.0
-40
-20
VIH
VIL
70%
2.0
45
Vdd-1.1
Vdd-1.9
+1.2
RMS Period Jitter
T_jitt
RMS Phase Jitter (random)
T_phj
+3.3
+2.5
100
6.0
6.0
+3.63
+2.75
+3.63
212.5
+10
+20
+25
+50
+2.0
+5.0
+85
+70
30%
250
10
10
55
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
ms
ms
%
+25°C
+25°C
Industrial
Extended Commercial
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time
ST
pin crosses
50% threshold.
Contact KDS for tighter duty cycle
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
Termination schemes in Figures 1 and 2 - XX ordering code
See last page for list of standard frequencies
LVPECL, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
+61
+1.6
300
1.2
1.2
1.2
0.6
+69
+35
+1.0
+100
+30
Vdd-0.7
Vdd-1.5
+2.0
500
115
1.7
1.7
1.7
0.85
mA
mA
μA
μA
mA
V
V
V
ps
ns
ps
ps
ps
ps
Excluding Load Termination Current, Vdd = +3.3V or +2.5V
OE = Low
OE = Low
ST
= Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, Vdd = +3.3V or +2.5V
f = 156.25 MHz, Vdd = +3.3V or +2.5V
f = 212.5 MHz, Vdd = +3.3V or +2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Excluding Load Termination Current, Vdd = +3.3V or +2.5V
OE = Low
See Figure 2
LVDS, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Idd
I_OE
VOD
+250
+47
+350
+55
+35
+450
mA
mA
mV
Daishinku Corp.
Rev. 1.06
1389 Shinzaike, Hiraoka-cho, Kakogawa, Hyogo 675-0194 Japan
+81-79-426-3211
www.kds.info
Revised October 3, 2014
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