Am29F010B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
22336
Revision
C
Amendment
+4
Issue Date
August 22, 2005
THIS PAGE INTENTIONALLY LEFT BLANK
Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 5.0 V ± 10% for read, erase, and program operations
— Simplifies system-level power requirements
■
Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
■
High performance
— 45 ns maximum access time
■
Low power consumption
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
■
Flexible sector architecture
— Eight 16 Kbyte sectors
— Any combination of sectors can be erased
— Supports full chip erase
■
Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
■
Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
■
Erase Suspend/Resume
— Supports reading data from a sector not
being erased
■
Minimum 1 million erase cycles guaranteed per
sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■
Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
22336
Rev:
C
Amendment/+4
Issue Date:
August 23, 2005
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only
Flash memory organized as 131,072 bytes. The
Am29F010B is offered in 32-pin PDIP, PLCC and
TSOP packages. The byte-wide data appears on
DQ0-DQ7. The device is designed to be pro-
grammed in-system with the standard system 5.0
Volt V
CC
supply. A 12.0 volt V
PP
is not required for
program or erase operations. The device can also
be programmed or erased in standard EPROM
programmers.
This device is manufactured using AMD’s 0.32
µm process technology, and offers all the fea-
tures and benefits of the Am29F010 and
Am29F010A.
The standard device offers access times of 45,
55, 70, 90, and 120 ns, allowing high-speed mi-
croprocessors to operate without wait states. To
eliminate bus contention the device has sepa-
rate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
The device requires only a
single 5.0 volt
power supply
for both read and write func-
tions. Internally generated and regulated
voltages are provided for the program and erase
operations.
The device is entirely command set compatible
with the
JEDEC single-power-supply Flash
standard.
Commands are written to the com-
mand register using standard microprocessor
write timings. Register contents serve as input
to an internal state machine that controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data needed
for the programming and erase operations.
Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the
program command sequence. This invokes the
Embedded Program
algorithm—an internal al-
gorithm that automatically times the program
pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase
command sequence. This invokes the
Embed-
ded Erase
algorithm—an internal algorithm
that automatically preprograms the array (if it is
not already programmed) before executing the
erase operation. During erase, the device auto-
matically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program
or erase operation is complete by reading the
DQ7 (Data# Polling) and DQ6 (toggle)
status
bits.
After a program or erase cycle has been
completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory
sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The
device is erased when shipped from the factory.
The
hardware data protection
measures in-
clude a low V
CC
detector automatically inhibits
write operations during power transitions. The
hardware sector protection
feature disables
both program and erase operations in any com-
bination of the sectors of memory, and is
implemented using standard EPROM
programmers.
The system can place the device into the
standby
mode.
Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce
the highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM
programming mechanism of hot electron
injection.
2
Am29F010B
August 23, 2005
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29F010B Device Bus Operations .................................9
DQ5: Exceeded Timing Limits ................................................ 18
DQ3: Sector Erase Timer ....................................................... 18
Table 5. Write Operation Status ..................................................... 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 19
Figure 5. Maximum Negative Overshoot Waveform ...................... 19
Figure 6. Maximum Positive Overshoot Waveform ........................ 19
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Output Disable Mode .............................................................. 10
Table 2. Am29F010B Sector Addresses Table ...............................10
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Test Setup ....................................................................... 22
Table 6. Test Specifications ........................................................... 22
Key to Switching Waveforms . . . . . . . . . . . . . . . 22
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Read Operations Timings ............................................... 23
Autoselect Mode ..................................................................... 10
Table 3. Am29F010B Autoselect Codes (High Voltage Method) ....11
Erase and Program Operations .............................................. 24
Figure 9. Program Operation Timings ............................................ 25
Figure 10. Chip/Sector Erase Operation Timings .......................... 25
Figure 11. Data# Polling Timings (During
Embedded Algorithms) ................................................................... 26
Figure 12. Toggle Bit Timings (During
Embedded Algorithms) ................................................................... 26
Sector Protection/Unprotection ............................................... 11
Hardware Data Protection ...................................................... 11
Low V
CC
Write Inhibit ......................................................................11
Write Pulse “Glitch” Protection ........................................................11
Logical Inhibit ..................................................................................11
Power-Up Write Inhibit ....................................................................11
Erase and Program Operations .............................................. 27
Alternate CE# Controlled Writes .................................................... 27
Figure 13. Alternate CE# Controlled Write
Operation Timings .......................................................................... 28
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data ................................................................ 12
Reset Command ..................................................................... 12
Autoselect Command Sequence ............................................ 12
Byte Program Command Sequence ....................................... 12
Figure 1. Program Operation ..........................................................13
Chip Erase Command Sequence ........................................... 13
Sector Erase Command Sequence ........................................ 13
Erase Suspend/Erase Resume Commands ........................... 14
Figure 2. Erase Operation ...............................................................14
Table 4. Am29F010B Command Definitions ...................................15
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 16
DQ7: Data# Polling ................................................................. 16
Figure 3. Data# Polling Algorithm ...................................................16
DQ6: Toggle Bit I .................................................................... 17
Reading Toggle Bit DQ6 ......................................................... 17
Figure 4. Toggle Bit Algorithm .........................................................17
Erase and Programming Performance . . . . . . . 28
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 29
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 29
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 30
PD 032—32-Pin Plastic DIP ................................................... 30
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 31
TS 032—32-Pin Standard Thin Small
Outline Package ..................................................................... 32
TSR 032—32-Pin Standard Thin Small
Outline Package ..................................................................... 33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
August 23, 2005
Am29F010B
3
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