DSC400
Low-Jitter, Configurable Quad Output Crystal-less™ Clock Generator
General Description
The DSC400 series of high performance quad
output crystal-less™ clock generator utilize a
proven silicon MEMS technology to provide
excellent
jitter
and
stability
while
incorporating additional device functionality.
The four outputs are controlled by separate
supply voltages to allow for high output
isolation. The frequencies of the outputs can
be identical or independently derived from a
common PLLs frequency sources.
The
DSC400 has provision for up to eight user-
defined
pre-programmed,
pin-selectable
output frequency combinations.
DSC400 is packaged in a 20-pin 5x3.2 mm
QFN package and available in temperature
grades from Ext. Commercial to Industrial.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Four format configurable outputs:
o
LVPECL, LVDS, HCSL, LVCMOS
Available Pin-Selectable frequency table
o
3 pins select 8 different combinations
Short Lead Times: 2 Weeks
Wide Freq. Range:
o
2.3 – 460 MHz
Miniature Footprint of 5x3.2mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Block Diagram
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
AEC-Q100 Automotive Qualified
Applications
Communications and Networks
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
HD/SD/SDI Video & Surveillance
Embedded and Industrial
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 1
DSC400 Low-Jitter, Configurable Quad Output Crystal-less™ Clock Generator
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD
NC
Pin
Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
O
O
Power
NA
Description
Output Enable; active high – See Table 1
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair 0 (off when in LVCMOS
True output of differential pair 0 or LVCMOS output 0
Complement output of differential pair 1 (off when in LVCMOS
True output of differential pair 1 or LVCMOS output 1
Power Supply
Leave unconnected or grounded
Output Enable; active high – See Table 1
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair 2 (off when in LVCMOS
True output of differential pair 2 or LVCMOS output 2
Complement output of differential pair 3 (off when in LVCMOS
True output of differential pair 3 or LVCMOS output 3
Power Supply
Leave unconnected or grounded
format)
format)
format)
format)
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 2
DSC400 Low-Jitter, Configurable Quad Output Crystal-less™ Clock Generator
Operational Description
The DSC400 is a quad output clock generator consisting of a MEMS resonator and support PLLs IC.
The four outputs are generated through independent 8-bit programmable dividers with internal pre-
programmed memory (OTP).
Customers also have the option to access eight different combinations of frequencies through three
input select lines or through I2C. Discera supports customer defined versions of the DSC400.
Contact factory with your frequencies and output formats requirements:
sales@discera.com
Factory configuration code assignment
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Ordering Code
Extension
Rxxxx
Example: R0001
Clk0 (MHz)
Fout1
125
Clk1 (MHz)
Fout2
156.56
Clk2 (MHz)
Fout3
156.56
Clk3 (MHz)
Fout4
50
Ordering
Information Example
DSC400-
4 3 2 1 R x x x x K I 1 T
T
4
T
4
4
4
4
4
CLK 3 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
ReelCLK
2 Output
Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK 1 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
CLK 0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Packing
T: Tape &
Stability
1: ±50ppm
2: ±25ppm
Temp Range
E: -20ºC to 70ºC
I: -40ºC to 85ºC
L: -40ºC to 105ºC
Package
K: 20 QFN
Frequency Code
Assigned by
factory
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 3
DSC400 Low-Jitter, Configurable Quad Output Crystal-less™ Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Notes:
1.
2.
3.
4.
5.
(Unless specified otherwise: T=25° C)
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
40
EN pin low – outputs are disabled
EN pin high – outputs are enabled
R
L
=50Ω,
Clk(0-3)=156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
Min.
2.25
Typ.
42
178
Max.
3.6
46
Unit
V
mA
mA
±10
±25
±50
±5
5
-
0.25xV
DD
5
20
ppm
ppm
ms
V
ns
ns
kΩ
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 4
DSC400 Low-Jitter, Configurable Quad Output Crystal-less™ Clock Generator
LVPECL Outputs
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
t
R
t
F
f
0
SYM
J
PER
J
PH
V
OH
V
OL
R
L
=50Ω
Single-Ended
20% to 80%
R
L
=50Ω
Single Frequency
Differential
F
O1
=F
O2
=156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.3
48
2.5
0.25
0.38
1.7
V
DD
-1.08
-
800
250
460
52
-
V
DD
-1.55
V
mV
ps
MHz
%
ps
RMS
2
ps
RMS
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
156MHz LVPECL
2.0
212MHz LVPECL
320MHz LVPECL
410MHz LVPECL
1.5
1.0
0.5
Phas e Jitter ( ps RM S)
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
LVPECL Phase jitter (integrated phase noise)
Output Waveform:
t
R
t
F
Output
Output
80
%
50%
20%
830 mv
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 5
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
