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SL1466
Wideband PLL FM Demodulator
Preliminary Information
DS 3979 2.2 August 1997
SL1466
The SL1466 is a wideband PLL FM demodulator, intended
primarily for application in satellite tuners.
The device contains all elements necessary, with the
exception of external local oscillator tank and loop filter
components, to form a complete PLL system operating at 403
or 480MHz.
An AFC system is provided, whose output signals can be
used to correct for any frequency drift at the head end local
oscillator.
GND
DIGF LO
DIGF HI
AFC SET
AFC WINDOW
OSC V CC
OSC +
OSC –
OSC GND
VCO GAIN SET
VIDEO DRIVE
VIDEO POL SELECT
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V CC
VIDEO FB+
VIDEO +
VIDEO –
VIDEO FB–
IF V CC
IF IPB
IF IP
IF GND
RF AGC SET
AGC TIME CONSTANT
IF AGC SET
NC
RF AGC CONTROL
FEATURES
I
Single chip PLL system for wideband FM
demodulation
I
Simple low component count application
I
Fully balanced low radiation design
I
High operating input sensitivity
I
2 stage AGC detect for control over internal and
external AGC stages
I
Low distortion video output drive
I
Video polarity invert
I
Digital AFC with window adjust
I
ESD protection (Normal ESD handling procedures
should be observed)
QP28
Fig.1 Pin connections - top view
APPLICATIONS
I
Satellite receiver systems
I
Data communications systems
ORDERING INFORMATION
SL1466/KG/QP1S
PHASE
DETECTOR
27
26
25
24
VIDEO FB+
VIDEO +
VIDEO –
VIDEO FB–
IF IP
IF IPB
21
22
AGC
AMP
AGC
DETECT
ON CHIP
VCO
11
12
VIDEO DRIVE
VIDEO
POLARITY
SELECT
S/H
AFC
NC
16
REF
4
AFC SET
NC
RF AGC CONTROL
28
1
13
15
5
2
3
14
NC
19
RF AGC
SET
18
17
7 8
LO
TANK
10
VCO
GAIN SET
AGC TIME IF
CONST
AGC
SET
AFC WINDOW
DIGF LO
DIGF HI
Vcc GND
Fig. 2 Block diagram
SL1466
ELECTRICAL CHARACTERISTICS
T
AMB
= -20°C to +80°C, V
CC
= +4.75 to +5.25V. These characteristics are guaranteed by either production test or design.
They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Pin
Min
Supply current, Icc
RF Section
Operating frequency
Input sensitivity
Input overload
Input Impedance
Internal AGC AMP range
VCO Section
VCO dF/dV (K
o
)
VCO supply sensitivity
VCO temperature sensitivity
Video section
Phase detector gain (K
d
)
Loop amplifier input
impedance
Video drive output swing
Video drive output
Impedance
Video drive luminance
non - linearity
Differential gain
Differential phase
Tilt
Base line distortion
Intermodulation
Signal/noise
Video polarity select input
Low
Video polarity select input
High
Video polarity switch
leakage current
Video polarity switch
leakage current
Positive to negative video
gain balance
AFC section
AFC window minimum
widths
AFC output high voltage
AFC output low voltage
2,3
2,3
V
CC
-0.4
0
0.44
V
CC
0.4
MHz
V
V
Deadband measured at 90% of
AFC high voltage
11
11
11
11
11
11
11
12
12
12
12
11
V
CC
10
10
1
2
±2
±2
1.0
-46
58
V
EE
0.5
-40
%
%
Deg
%
dB
dB
dB
V
V
µA
µA
dB
75Ω load
75Ω load
75Ω load
75Ω load
75Ω load
75Ω load, see note 1
75Ω load, see note 2
Negative polarity
Positive polarity
V
CC
=5.25V
V
CC
=5.25V
V
in
=0V
V
in
=5.25V
11
11
11
0.5
570
0.9
1.8
100
V/rad
Ω
Vp-p
Vp-p
Ω
Differential loop filter
R1 in note on loop parameters
Into 75Ω, 18MHz frequency deviation
Into 1KΩ, 18MHz frequency deviation
At 27°C
6,23,28
21, 22
21, 22
21, 22
21, 22
50
10
6,7,8,9
7,8
54
1.0
0.05
0
Value
Typ
65
480
-60
-7
75
Max
mA
MHz
dBm
dBm
Ω
dB
MHz/V
MHz/V
MHz/°C
At 27°C
0-55°C, V
CC
=5V, 750ppmNTC, 0.5pF
tuning cap.
At 27°C
Units
Conditions
2
SL1466
NOTE:
1. Product of input modulation f
1
at 4.43MHz p-p deviation and f
2
at 6MHz, 2MHz p-p deviation, (PAL
chroma and sound subcarriers).
2. Ratio of luminance bar amplitude (100% white), 13.5MHz p-p deviation, to output rms noise in 6MHz
bandwidth with no input modulation.
3. The above characteristics were measured in the Application circuit shown in Fig.10, with an input power of
-50dBm andƒ(RFIN) =480MHz, unless otherwise stated.
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V
EE
at 0V
Characteristic
Min
Max
Units
Conditions
Supply voltage
RF input voltage
Storage temperature
Junction temperature
QP 28 package thermal
resistant, chip to ambient
QP 28 package thermal
resistance, chip to case
ESD protection
-0.3
-55
7
2.5
125
150
93
34
V
Vp-p
°C
°C
°C/W
°C/W
kV
Mil std 883B method 30115 cat 1.
2
PIN DESCRIPTION
PIN NO
1
2
3
4
5
PIN NAME
GND
DIGFLO
DIGFHI
AFCSET
AFCWINDOW
DESCRIPTION
Chip ground
Flag = high when F (local oscillator) < F (IFIN) - F (WINDOW)/2
Flag = high when F (local oscillator) >F (IFIN) + F (WINDOW)/2
Connected to V
CC
Control input current sink sets width of AFCWINDOW
F =2250 K
o
x I where I is the AFCWINDOW current
F is the window width and K
o
is the VCO gain
6
7
8
9
10
11
12
13
14
15
16
17
18
OSC V
CC
OSC+
OSC-
OSC GND
VCO GAIN SET
VIDEO DRIVE
VIDEO POL SELECT
NC
NC
RF AGC CONTROL
NC
IF AGC SET
AGC TIME CONSTANT
Connect to V
CC
via 6k8 Ohm resistor
Control input current source. Pulse at carrier frequency F(IFIN) with
mark/space proportional to applied device AGC gain.
Use external R-C to set time constant. 47K, 100nF
Control output current to tuner AGC control port. See Fig. 4.
Oscillator V
CC
External tank
External tank
Oscillator ground
Control voltage input to set VCO GAIN. Connect to V
CC
Video output (1KΩ, 1.8V p-p)
Control voltage input to set Video polarity. 0 Volts = inverted,
5 Volt = normal
(Note units are MHz, Amps and Volts)
3
SL1466
PIN DESCRIPTION
PIN NO
19
20
21
22
23
24
25
26
27
28
PIN NAME
RF AGC SET
IF GND
IF IP
IF IPB
IF V
CC
VIDEO FB-
VIDEO-
VIDEO+
VIDEO FB+
V
CC
DESCRIPTION
IF stage ground
IF input (preferred input for single ended use)
IF input
IF stage V
CC
Loop amp negative input. Connected to VIDEO + via loop network
Loop amp negative output
Loop amp positive output
Loop amp positive input. Connected to VIDEO- via loop network
Chip V
CC
(Note units are MHz, Amps and Volts)
Connect to V
CC
via 1.8K resistor
FUNCTIONAL DESCRIPTION
The SL1466 is a wideband PLL FM demodulator,
optimised for application in satellite receiver systems and
requiring a minimal external component count. It contains all
the elements required for the construction of a phase locked
loop circuit, with the exception of tuning components for the
local oscillator. Also included is an AFC detector circuit for
generation of error signals to correct for any frequency drift in
the outdoor unit local oscillator. A block diagram is shown in
Fig. 2 and a typical application in Fig. 6.
The internal pin connections are shown in Fig. 1.
In normal applications the second satellite IF of typically
403.2 or 479.5 MHz is fed to the RF preamplifier, which
contains a two stage level detect circuit. This generates two
AGC signals, one of which controls the gain of the internal IF
amplifier stage and one which can be used for controlling the
gain of an external RF preamplifier so maintaining a fixed level
to the input of the phase detector for optimum threshold,
performance. The typical AGC curves are shown in Fig. 4.
The output of the preamplifier is fed to the mixer section
which is of a balanced design for low radiation. In this stage the
IF signal is mixed with the local oscillator signal, which is
generated by an on board oscillator.
The oscillator is tuned internally, requiring only an external
fixed LC tank and is optimised for high linearity over the normal
deviation range. Typical frequency versus video drive voltage
response for the oscillator is shown in Fig. 8. This response
was measured with a modulated carrier. The compensated
oscillator temperature stability is typically 0.05MHz/°C.
The gain of the oscillator is nominally Ko = 54MHz/Volt.
Note: Because there is a x3 amplifier in the video output
section, the overall chip gain (MHz/V) is one third of the VCO
gain or18MHz/Volt. The gain may be set accurately by means
of potential divider connected to Pin 10. (+4.5V)
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop amplifier
transfer characteristics. The output of the loop amplifier is
referenced so as to eliminate V
CC
dependence of the VCO.
The loop amplifier drives a buffer amplifier, which can be
connected to a 75 Ohm load or a high impedance stage to give
greater linearity and approximately 6dB higher demodulated
signal. The video polarity can be inverted depending on the
sense of the video polarity select input; open circuit or a
resistor to V
CC
gives positive video whereas a resistor to V
EE
gives negative video.
R2
PHASE DETECTOR
GAIN = Kd VOLT/RAD
RF INPUT
R1
C1
X3
VIDEO DRIVE
VCO
VCO GAIN = Ko RAD/SEC/VOLT
VIDEO
Fig. 3 Design of PLL loop parameters
4
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