SRAM
Austin Semiconductor, Inc.
64K x 1 SRAM
SRAM MEMORY ARRAY
MT5C6401
PIN ASSIGNMENT
(Top View)
22-Pin DIP (C)
(300 MIL)
A0
A1
A2
A3
A4
A5
A6
A7
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
Vcc
A15
A14
A13
A12
A11
A10
A9
A8
D
CE\
AVAILABLE AS MILITARY
SPECIFICATIONS
•
•
SMD 5962-86015
MIL-STD-883
FEATURES
• Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications, Austin
Semiconductor offers chip enable (CE\) on all organizations.
This enhancement can place the outputs in High-Z for
additional flexibility in system design. The X1 configuration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ goes LOW.
The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil)
MARKING
-12
-15
-20
-25
-35
-45*
-55*
-70*
C
No. 105
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 35ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C6401
Rev. 1.0 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
MT5C6401
A
A
ROW DECODER
I/O CONTROL
D
A
A
A
A
A
Q
65,536-BIT
MEMORY ARRAY
CE\
(LSB)
WE\
POWER
DOWN
COLUMN DECODER
(LSB)
A A A A A A A A A
TRUTH TABLE
MODE
STANDBY
READ
WRITE
CE\
H
L
L
WE\
X
H
L
DQ
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
MT5C6401
Rev. 1.0 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Input Relative to Vss................-2.0V to +7.0V
Voltage on Vcc Supply Relative to Vss............-1.0V to +7.0V
Voltage Applied to Q.........................................-1.0V to +7.0V
Storage Temperature…...................................-65
o
C to +150
o
C
Power Dissipation.................................................................1W
Max Junction Temperature............................................+175°C
Lead Temperature (soldering 10 seconds)...................+260
o
C
Short Circuit Output Current...........................................50mA
MT5C6401
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYM
V
IH
V
IL
MIN
2.2
-0.5
-10
-10
2.4
---
MAX
UNITS NOTES
Vcc+1.0V
V
1
0.8
10
10
---
0.4
MAX
-20
110
V
µA
µA
V
V
1, 2
0V < V
IN
< V
CC
Outputs Disabled
0V < V
OUT
< V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
Output Open
CE\ > V
IH
; V
CC
= MAX
f = 1/t
RC
(MIN) Hz
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
IL
I
IL
O
V
OH
V
OL
SYM
I
cc
-12
140
1
1
PARAMETER
Power Supply
Current: Operating
Power Supply
Current: Standby
-15
125
-25
100
-35
90
UNITS NOTES
mA
3
I
SBT1
45
41
36
33
30
mA
I
SBT2
25
25
25
25
25
mA
CE\ > (V
CC
-0.2); V
CC
= MAX
All Other Inputs < 0.2V
or > (V
CC
- 0.2V), f = 0 Hz
I
SBC2
5
5
5
5
5
mA
CAPACITANCE
DESCRIPTION
Input Capacitance
Output Capacitance
CONDITIONS
T
A
= 25 C, f = 1MHz
Vcc = 5V
o
SYM
C
I
C
O
MAX
6
7
UNITS
pF
pF
NOTES
4
4
MT5C6401
Rev. 1.0 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C6401
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-12
-15
-20
-25
-35
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
12
10
2
2
7
0
12
12
10
10
0
0
10
7
0
2
0
15
12
12
0
0
12
8
0
2
0
0
15
20
15
15
0
0
15
10
0
2
0
2
2
8
0
20
25
20
20
0
0
20
12
0
2
0
15
15
13
2
2
10
0
25
35
25
25
0
0
25
15
0
2
0
20
20
15
2
2
12
0
35
25
25
20
2
2
15
35
35
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6, 7
6
7
8
10
15
7
6, 7
MT5C6401
Rev. 1.0 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
+5V
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
MT5C6401
+5V
480
480
Q
255
5 pF
Q
255
30pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is sampled.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
HZCE
and t
HZWE
are specified with CL = 5pF as in
Fig. 2. Transition is measured ±500mV typical from steady
state voltage, allowing for actual tester RC time constant.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = READ Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
7.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
V
CC
= 3V
CONDITIONS
SYM
V
DR
I
CCDR
I
CCDR
t
CDR
t
R
MIN
2
---
---
0
t
RC
MAX
---
300
500
---
---
UNITS
V
µA
µA
ns
ns
4
4, 11
NOTES
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
CE\
MT5C6401
Rev. 1.0 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
4321
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3
V
IH
V
IL
V
DR
4216
3326
32
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3326
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