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NSBA124XDXV6T1

产品描述trans prebias dual pnp sot563
产品类别半导体    分立半导体   
文件大小133KB,共12页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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NSBA124XDXV6T1概述

trans prebias dual pnp sot563

NSBA124XDXV6T1规格参数

参数名称属性值
Datasheets
NSBA114EDXV6T1,5 Series
Product Photos
SOT-563-6_463A
PCN Obsolescence/ EOL
Multiple Devices 01/Jul/2005
Standard Package4,000
CategoryDiscrete Semiconductor Products
FamilyTransistors (BJT) - Arrays, Pre-Biased
系列
Packaging
Tape & Reel (TR)
Transistor Type2 PNP - Pre-Biased (Dual)
Current - Collector (Ic) (Max)100mA
Voltage - Collector Emitter Breakdown (Max)50V
Resistor - Base (R1) (Ohms)22k
Resistor - Emitter Base (R2) (Ohms)47k
DC Current Gain (hFE) (Min) @ Ic, Vce80 @ 5mA, 10V
Vce Saturation (Max) @ Ib, Ic250mV @ 1mA, 10mA
Current - Collector Cutoff (Max)500nA
Power - Max500mW
Mounting TypeSurface Mou
封装 / 箱体
Package / Case
SOT-563, SOT-666
Supplier Device PackageSOT-563
Other NamesNSBA124XDXV6T1OS

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NSBA114EDXV6T1,
NSBA114EDXV6T5
Preferred Devices
Dual Bias Resistor
Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBA114EDXV6T1
series, two BRT devices are housed in the SOT−563 package which is
ideal for low−power surface mount applications where board space is
at a premium.
(3)
R
1
Q
1
Q
2
R
2
(4)
R
1
(5)
(6)
http://onsemi.com
(2)
R
2
(1)
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch Tape and Reel
Lead Free Solder Plating
6
54
23
1
SOT−563
CASE 463A
PLASTIC
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted, common for Q
1
and Q
2
)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
−50
−50
−100
Unit
Vdc
Vdc
mAdc
xx = Specific Device Code
(see table on page 2)
D = Date Code
Symbol
P
D
Max
357
(Note 1)
2.9
(Note 1)
350
(Note 1)
Max
500
(Note 1)
4.0
(Note 1)
250
(Note 1)
−55 to
+150
Unit
mW
mW/°C
°C/W
NSBA114EDXV6T5 SOT−563
Unit
mW
xx D
MARKING DIAGRAM
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
Derate above 25°C
Thermal Resistance Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
Derate above 25°C
Thermal Resistance Junction-to-Ambient
Junction and Storage
Temperature Range
1. FR−4 @ Minimum Pad
R
qJA
T
J
, T
stg
T
A
= 25°C
R
qJA
T
A
= 25°C
ORDERING INFORMATION
Device
Package
Shipping
4 mm pitch
4000/Tape & Reel
2 mm pitch
8000/Tape & Reel
NSBA114EDXV6T1 SOT−563
Symbol
P
D
DEVICE MARKING INFORMATION
mW/°C
°C/W
°C
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2004
1
January, 2004 − Rev. 3
Publication Order Number:
NSBA114EDXV6/D

 
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