SM560
Spread Spectrum Clock Generator
Features
•
•
•
•
•
•
•
•
•
25- to 108-MHz operating frequency range
Wide (9) range of spread selections
Accepts clock and crystal inputs
Low power dissipation
3.3V = 85 mw (50 MHz)
Frequency Spread disable function
Center Spread modulation
Low cycle-to cycle jitter
Eight-pin SOIC package
Applications
• VGA controllers
• LCD panels and monitors
• Printers and multi-function devices (MFP)
Benefits
• Peak electromagnetic interference (EMI) reduction
by 8 to 16 dB
• Fast time to market
• Cost reduction
Block Diagram
Pin Configuration
250 K
Xin/
CLK
1
4 pf
REFERENCE
DIVIDER
PD
CP
LF
Xin/CLK
VDD
VSS
SSCLK
FEEDBACK
DIVIDER
VCO
1
2
3
4
8
Xout
S0
S1
SSCC
SM560
7
6
5
MODULATION
CONTROL
Xout
8
8 pF
VDD
VSS
2
INPUT
DECODER
LOGIC
DIVIDER
AND MUX
3
4
SSCLK
5
6
7
SSCC
S1
S0
Cypress Semiconductor Corporation
Document #: 38-07020 Rev. *E
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 25, 2004
SM560
Pin Definitions
Pin
1
2
3
4
5
6
7
8
Name
Xin/CLK
VDD
GND
SSCLK
SSCC
S1
S0
Xout
Type
I
P
P
O
I
I
I
O
Positive power supply.
Power supply ground.
Modulated clock output.
Spread Spectrum Clock Control (Enable/Disable) function.
SSCG function is enabled
when input is high and disabled when input is low. This pin is pulled high internally.
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See
Figure 1.
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See
Figure 1.
Oscillator output pin connected to crystal.
Leave this pin unconnected If an external
clock drives Xin/CLK.
Description
Clock or Crystal connection input.
Refer to
Table 1
for input frequency range selection.
Functional Description
The Cypress SM560 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing Electro Magnetic
Interference (EMI) found in today’s high-speed digital
electronic systems.
The SM560 uses a Cypress-proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of Clock (SSCLK1) is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
The SM560 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1digital inputs. These inputs use three (3) logic states
including High (H), Low (L) and Middle (M) logic levels to select
Table 1. Frequency and Spread% Selection (Center Spread)
2 5 – 5 4 M H z (L o w R a n g e )
In p u t
F re q u e n c y
(M H z )
25 – 35
35 – 40
40 – 45
45 – 50
50 – 54
S1=M
S0=M
(% )
3 .8
3 .5
3 .2
3 .0
2 .8
S1=M
S0=0
(% )
3 .2
3 .0
2 .8
2 .6
2 .4
S1=1
S0=0
(% )
2 .8
2 .5
2 .4
2 .2
2 .0
S1=0
S0=0
(% )
2 .3
2 .1
1 .9
1 .8
1 .7
S1=0
S0=M
(% )
1 .9
1 .7
1 .6
1 .5
1 .4
S e le c t th e
F re q u e n c y a n d
C e n te r S p re a d %
d e s ire d an d th en
set S 1, S 0 as
in d ic a te d .
one of the nine available Frequency Modulation and Spread%
ranges. Refer to
Table 1
for programming details.
The SM560 is optimized for SVGA (40 MHz) and XVGA (65
MHz) Controller clocks and also suitable for the applications
with the frequency range of 25 to 108 MHz.
A wide range of digitally selectable spread percentages is
made possible by using three-level (High, Low and Middle)
logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The SM560 is available in an eight-pin SOIC package with a 0
to 70°C operating temperature range.
5 0 – 1 0 8 M H z (H ig h R a n g e )
In p u t
F re q u e n c y
(M H z )
50 – 60
60 – 70
70 – 80
80 – 100
100 – 108
S1=1
S0=M
(% )
2 .5
2 .4
2 .3
2 .0
1 .8
S1=0
S0=1
(% )
1 .9
1 .8
1 .6
1 .4
1 .3
S1=1
S0=1
(% )
1 .2
1 .1
1 .1
1 .0
0 .8
S1=M
S0=1
(% )
1 .0
0 .9
0 .9
0 .8
0 .6
S e le c t th e
F re q u e n c y a n d
C e n te r S p re a d %
d e s ire d an d th en
set S 1, S 0 as
in d ic a te d .
Document #: 38-07020 Rev. *E
Page 2 of 8
SM560
Tri-level Logic
With binary logic, four states can be programmed with two
control lines, whereas Tri-level Logic can program nine logic
states using two control lines. Tri-level Logic in the SM560 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0.” Pins 6 and 7 of the SM560
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
VDD = 3.3 VDC
“1” (One). Each of these states has a defined voltage range
that is interpreted by the SM560 as a “0,” “M,” or “1” logic state.
Refer to
Table 2
for voltage ranges for each logic state. By
using two equal value resistors (typically 20K) the “M” state
can be easily programmed. Pins 6 or 7 can be tied directly to
ground or VDD for Logic “0” or “1” respectively.
VDD = 3.3 VDC
VDD = 3.3 VDC
SM560
20K
SM560
SM560
7
1.65 VDC
7
7
6
0 VDC
20K
6
6
5
5
5
EX. 1
EX. 2
EX. 3
Figure 1.
Document #: 38-07020 Rev. *E
Page 3 of 8
SM560
Absolute Maximum Ratings
[1]
Supply Voltage (V
DD
): .................................... –0.5V to +6.0V
DC Input Voltage:..................................–0.5V to VDD + 0.5V
Junction Temperature ................................. –40°C to +140°C
Operating Temperature:...................................... 0°C to 70°C
Storage Temperature .................................. –65°C to +150°C
Static Discharge Voltage (ESD).......................... 2,000V-Min.
Table 2. DC Electrical Characteristics:
V
DD
= 3.3V, Temp. = 25°C and C
L
(Pin 4) = 15 pF, unless otherwise noted
Parameter
V
DD
V
INH
V
INM
V
INL
V
OH1
V
OH2
V
OL1
V
OL2
Cin1
Cin2
Cin2
I
DD1
I
DD2
Description
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Input Capacitance
Input Capacitance
Input Capacitance
Power Supply Current
Power Supply Current
±10%
S0 and S1 only
S0 and S1 only
S0 and S1 only
I
OH
= 6 mA
I
OH
= 20 mA
I
OH
= 6 mA
I
OH
= 20 mA
Xin/CLK (Pin 1)
Xout (Pin 8)
S0, S1, SSCC (Pins 7,6,5)
F
IN
= 40 MHz
F
IN
= 65 MHz
3
6
3
4
8
4
30
35
Conditions
Min.
2.97
0.85V
DD
0.40V
DD
0.0
2.4
2.0
0.4
1.2
5
10
5
40
45
Typ.
3.3
V
DD
0.50V
DD
0.0
Max.
3.63
V
DD
0.60V
DD
0.15V
DD
Unit
V
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
Table 3. Electrical Timing Characteristics:
V
DD
= 3.3V, T = 25°C and C
L
= 15 pF, unless otherwise noted
Parameter
ICLKFR
Trise
Tfall
DTYin
DTYout
JCC
Description
Input Clock Frequency Range
Clock Rise Time (Pin 4)
Clock Fall Time (Pin 4)
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter
Conditions
V
DD
= 3.30V
SSCLK1 @ 0.4 – 2.4V
SSCLK1 @ 0.4 – 2.4V
XIN/CLK (Pin 1)
SSCLK1 (Pin 4)
Fin = 25 – 108 MHz
Min.
25
1.2
1.2
20
45
-
1.4
1.4
50
50
125
Typ.
Max.
108
1.6
1.6
80
55
175
Unit
MHz
ns
ns
%
%
ps
SSCG Theory of Operation
The SM560 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the SM560 becomes a Low EMI clock generator.
The theory and detailed operation of the SM560 will be
discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multi-layer PCBs, etc. The SM560 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The SM560 takes a narrow band
digital reference clock in the range of 25–108 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following:
Note:
1.
Single Power Supply:
The Voltage on any input or I/O pin cannot exceed the power pin during power up.
Document #: 38-07020 Rev. *E
Page 4 of 8
SM560
Clock Frequency = fc = 65MHz
Clock Period = Tc =1/65 MHz = 15.4 ns
50 %
50 %
can see a 6.48-dB reduction in the peak RF energy when using
the SSCG clock.
Tc = 15.4 ns
Modulation Rate
Spectrum Spread Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmr.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The SM560 and SM561
have a fixed divider count, as listed below.
If this clock is applied to the Xin/CLK pin of the SM560, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition from f1 to f2, the amount of time and sweep
waveform play a very important role in the amount of EMI
reduction realized from an SSCG clock.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. The left side of
Figure 2
shows the modulation profile of a 65-MHz SSCG clock. Notice
that the actual sweep waveform is not a simple sine or
sawtooth waveform. The right side of
Figure 2
is a scan of the
same SSCG clock using a spectrum analyzer. In this scan you
Device
SM560
SM561
Cdiv
1166
2332
(All Ranges)
(All Ranges)
SM560
65 MHz
S1 = 1, S0 = M
Example:
Device =
Fin
=
Range =
Then;
Modulation Rate = Fmod = 65 MHz/1166 = 55.8 kHz.
Spectrum2.46%
Modulation Profile
BW = Analyzer
-6.58 dB
Figure 2. SSCG Clock, SM560, Fin = 65 MHz
Document #: 38-07020 Rev. *E
Page 5 of 8
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