Note: Extended+ should not be used for Automotive.
Advanced Security Protection
-
Software and Hardware Write Protection
-
Advanced Sector/Block Protection
-
Top/Bottom Block Protection
-
Power Supply Lock Protection
-
4x256 Byte Dedicated Security Area
with OTP User-lockable Bits
-
128 bit Unique ID for Each Device
(Call Factory)
Industry Standard Pin-out & Packages
-
M =16-pin SOIC 300mil
-
L = 8-contact WSON 8x6mm
-
G = 24-ball TFBGA 6x8mm (4x6 ball array)
(1)
-
H = 24-ball TFBGA 6x8mm (5x5 ball array)
(1)
-
KGD (Call Factory)
Note: For the additional RESET# pin (or ball) option, call
Factory
Integrated Silicon Solution, Inc.- www.issi.com
Rev.00C
10/29/2015
2
IS25LP256A/128A
IS25WP256A/128A
GENERAL DESCRIPTION
The IS25LP256A/128A and IS25WP256A/128A Serial Flash memory offers a versatile storage solution with high
flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is
for systems that require limited space, a low pin count, and low power consumption. The device is accessed
through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock
(SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock
frequencies of up to 166MHz allow for equivalent clock rates of up to 664MHz (166MHz x 4) which equates to
83Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)
commands that transfer addresses and read data on both edges of the clock. These transfer rates can
outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place)
operation.
The memory array is organized into programmable pages of 256 bytes. This family supports page program
mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)
supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors,
32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a
high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data
retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the
status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Mutil I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode
will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Quad I/O QPI
The device enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode uses four IO
pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI and SO pins
become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during QPI
mode. Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or
Hardware/Software Reset can also return the device into the standard SPI mode.
DTR
In addition to SPI and QPI features, the device also supports SPI DTR READ. SPI DTR allows high data
throughput while running at lower clock frequencies. SPI DTR READ mode uses both rising and falling edges of
the clock to drive output, resulting in reducing input and output cycles by half.
Programmable drive strength and Selectable burst setting.
The device offers programmable output drive strength and selectable burst (wrap) length features to increase the
efficiency and performance of READ operation. The driver strength and burst setting features are controlled by
setting the Read Registers. A total of six different drive strengths and four different burst sizes (8/16/32/64 Byte)
are available for selection.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.00C
10/29/2015
3
IS25LP256A/128A
IS25WP256A/128A
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................................... 3
TABLE OF CONTENTS ........................................................................................................................................ 4
随着半导体技术的不断进步（按照摩尔定律），MCU内部集成的逻辑功能外设越来越多，存储器也越来越大。消费者对于汽车节能（经济和法规对排放的要求）型、舒适性、互联性、安全性（功能安全和信息安全）的要求越来越高，特别是近年来新能源电动车、车联网和自动驾驶技术的兴起，更大大加速了汽车电子技术的发展。汽车电子ECU（Electronic Control Unit--电控单元）集成的功能日益复杂，为了应对软...[详细]
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
