F
EATURES
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Four 16C950 High performance UART channels
8/32-bit Pass-through Local Bus
IEEE1284 EPP parallel port
Multi-function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
UARTs fully software compatible with 16C550-type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
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•
•
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•
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OX16PCI954
Integrated Quad UART
and PCI interface
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
9-bit data framing as well as 5,6,7 and 8
12 multi-purpose IO pins which can be configured as
interrupt input pins
Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Operation via IO or memory mapping.
Detection of bad data in the receiver FIFO
5.0V operation
160 TQFP package
D
ESCRIPTION
The OX16PCI954 is a single chip solution for PCI-based
serial and parallel expansion add-in cards. It is a dual
function PCI device, where function 0 offers four ultra-high
performance OX16C950 UARTs, and function 1 is
configurable to offer either an 8 bit Local Bus or a bi-
directional parallel port. Serial port cards with up to 8 ports
(or with 4 serial ports and a parallel port) can be designed
without redefining any device or timing parameters.
Each channel in the OX16PCI954, the fastest available
PC-compatible UART, offers data rates up to 15Mbps and
128-deep transmitter and receiver FIFOs. Deep FIFOs
reduce CPU overhead and allow utilisation of higher data
rates. Each channel is software compatible with the widely
used industry-standard 16C550 devices and compatibles
as well as the OX16C95x family of high performance
UARTs. In addition to increased performance and FIFO
size, the UARTs also provide the full set of OX16C95x
enhanced features including automated in-band flow
control, readable FIFO levels etc.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. For
applications that do not require the internal parallel port or
the local Bus, card designers can assign a Subsystem
Vendor ID and a Subsystem ID using 32 input pins. If the
UARTs are not required, the Local Bus can be extended
from 8-bit operation to a full 32-bit pass-through interface.
For full flexibility, all the default register values can be
overwritten using an optional Microwire
TM
serial EEPROM.
To enhance device driver efficiency and reduce interrupt
latency, internal UARTs have multi-port features such as
shadowed FIFO fill levels, a global interrupt source register
and Good-Data Status, readable in four adjacent DWORD
registers visible to logical functions in IO space and
memory space.
Expansion of serial cards beyond four channels is possible
using the 8-bit pass-through Local Bus function. The
addressable space can be increased up to 256 bytes, and
divided into four chip-select regions. In 32-bit mode the bus
can map up to 16kb of Memory address space. This
flexible expansion scheme caters for cards with up to 20
serial ports using external 16C950, 16C952, 16C954 or
compatible devices, for composite applications such as
combined serial and parallel port expansion cards.
The OX16PCI954 also provides an IEEE1284 EPP parallel
port which fully supports the existing Centronics interface.
The parallel port can be enabled in place of the Local Bus.
Oxford Semiconductor Ltd.
69 Milton Park, Abingdon, Oxon, OX14 4RX, UK
Tel: +44 (0)1235 824900
Fax: +44(0)1235 821141
©
Oxford Semiconductor 1999
OX16PCI954 Data Sheet Revision 1.3 – Feb. 1999
Part No. OX16PCI954-TQC60-A
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
C
ONTENTS
FEATURES ..........................................................................................................................................................1
DESCRIPTION.....................................................................................................................................................1
CONTENTS..........................................................................................................................................................2
1
2
3
4
5
6
6.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.5
6.6
6.6.1
6.6.2
PERFORMANCE COMPARISON...............................................................................................................5
BLOCK DIAGRAM ......................................................................................................................................6
PIN INFORMATION .....................................................................................................................................7
PIN DESCRIPTIONS ...................................................................................................................................8
CONFIGURATION & OPERATION ..........................................................................................................13
PCI TARGET CONTROLLER ...................................................................................................................14
OPERATION ............................................................................................................................................................. 14
CONFIGURATION SPACE........................................................................................................................................ 14
PCI CONFIGURATION SPACE REGISTER MAP................................................................................................... 15
ACCESSING LOGICAL FUNCTIONS ........................................................................................................................ 16
PCI ACCESS TO INTERNAL UARTS..................................................................................................................... 16
PCI ACCESS TO 8-BIT LOCAL BUS...................................................................................................................... 16
PCI ACCESS TO PARALLEL PORT ...................................................................................................................... 17
PCI ACCESS TO 32-BIT LOCAL BUS.................................................................................................................... 17
ACCESSING LOCAL CONFIGURATION REGISTERS .............................................................................................. 18
LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ..................................................... 18
MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ......................................................... 19
LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08):............................................................... 20
LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): .............................................................. 22
UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10) ........................................................................................ 23
UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14).................................................................................. 23
UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)........................................................................... 24
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ............................................. 25
PCI INTERRUPTS ..................................................................................................................................................... 26
POWER MANAGEMENT........................................................................................................................................... 27
POWER MANAGEMENT OF FUNCTION 0............................................................................................................ 27
POWER MANAGEMENT OF FUNCTION 1............................................................................................................ 28
OPERATION – MODE SELECTION........................................................................................................................... 29
450 MODE ............................................................................................................................................................ 29
550 MODE ............................................................................................................................................................ 29
EXTENDED 550 MODE......................................................................................................................................... 29
750 MODE ............................................................................................................................................................ 29
650 MODE ............................................................................................................................................................ 29
950 MODE ............................................................................................................................................................ 30
REGISTER DESCRIPTION TABLES ......................................................................................................................... 31
RESET CONFIGURATION ........................................................................................................................................ 34
HARDWARE RESET ............................................................................................................................................. 34
SOFTWARE RESET.............................................................................................................................................. 34
TRANSMITTER AND RECEIVER FIFOS ................................................................................................................... 35
FIFO CONTROL REGISTER ‘FCR’ ........................................................................................................................ 35
LINE CONTROL & STATUS...................................................................................................................................... 36
FALSE START BIT DETECTION ........................................................................................................................... 36
Page 2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.2
7.3
7.3.1
7.3.2
7.4
7.4.1
7.5
7.5.1
INTERNAL OX16C950 UARTS ................................................................................................................29
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
7.5.2
LINE CONTROL REGISTER ‘LCR’ ........................................................................................................................ 36
7.5.3
LINE STATUS REGISTER ‘LSR’............................................................................................................................ 37
7.6
INTERRUPTS & SLEEP MODE................................................................................................................................. 38
7.6.1
INTERRUPT ENABLE REGISTER ‘IER’................................................................................................................. 38
7.6.2
INTERRUPT STATUS REGISTER ‘ISR’................................................................................................................. 39
7.6.3
INTERRUPT DESCRIPTION.................................................................................................................................. 39
7.6.4
SLEEP MODE ....................................................................................................................................................... 40
7.7
MODEM INTERFACE................................................................................................................................................ 40
7.7.1
MODEM CONTROL REGISTER ‘MCR’.................................................................................................................. 40
7.7.2
MODEM STATUS REGISTER ‘MSR’ ..................................................................................................................... 41
7.8
OTHER STANDARD REGISTERS............................................................................................................................. 41
7.8.1
DIVISOR LATCH REGISTERS ‘DLL & DLM’ .......................................................................................................... 41
7.8.2
SCRATCH PAD REGISTER ‘SPR’......................................................................................................................... 41
7.9
AUTOMATIC FLOW CONTROL ................................................................................................................................ 42
7.9.1
ENHANCED FEATURES REGISTER ‘EFR’ ........................................................................................................... 42
7.9.2
SPECIAL CHARACTER DETECTION .................................................................................................................... 43
7.9.3
AUTOMATIC IN-BAND FLOW CONTROL.............................................................................................................. 43
7.9.4
AUTOMATIC OUT-OF-BAND FLOW CONTROL .................................................................................................... 43
7.10 BAUD RATE GENERATION...................................................................................................................................... 44
7.10.1
GENERAL OPERATION........................................................................................................................................ 44
7.10.2
CLOCK PRESCALER REGISTER ‘CPR’................................................................................................................ 44
7.10.3
TIMES CLOCK REGISTER ‘TCR’ .......................................................................................................................... 44
7.10.4
EXTERNAL 1X CLOCK MODE .............................................................................................................................. 46
7.10.5
CRYSTAL OSCILLATOR CIRCUIT ........................................................................................................................ 46
7.11 ADDITIONAL FEATURES ......................................................................................................................................... 46
7.11.1
ADDITIONAL STATUS REGISTER ‘ASR’............................................................................................................... 46
7.11.2
FIFO FILL LEVELS ‘TFL & RFL’............................................................................................................................. 47
7.11.3
ADDITIONAL CONTROL REGISTER ‘ACR’ ........................................................................................................... 47
7.11.4
TRANSMITTER TRIGGER LEVEL ‘TTL’ ................................................................................................................ 48
7.11.5
RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ................................................................................................. 48
7.11.6
FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .............................................................................................................. 48
7.11.7
DEVICE IDENTIFICATION REGISTERS................................................................................................................ 48
7.11.8
CLOCK SELECT REGISTER ‘CKS’ ....................................................................................................................... 49
7.11.9
NINE-BIT MODE REGISTER ‘NMR’....................................................................................................................... 49
7.11.10 MODEM DISABLE MASK ‘MDM’............................................................................................................................ 50
7.11.11 READABLE FCR ‘RFC’.......................................................................................................................................... 50
7.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.............................................................................................................. 50
8
8.1
8.2
8.3
LOCAL BUS...............................................................................................................................................51
OVERVIEW ............................................................................................................................................................... 51
OPERATION ............................................................................................................................................................. 51
CONFIGURATION & PROGRAMMING...................................................................................................................... 52
OPERATION AND MODE SELECTION ..................................................................................................................... 53
SPP MODE ........................................................................................................................................................... 53
PS2 MODE............................................................................................................................................................ 53
EPP MODE ........................................................................................................................................................... 53
ECP MODE (NOT SUPPORTED) .......................................................................................................................... 53
PARALLEL PORT INTERRUPT ................................................................................................................................ 53
REGISTER DESCRIPTION........................................................................................................................................ 54
PARALLEL PORT DATA REGISTER ‘PDR’ ........................................................................................................... 54
DEVICE STATUS REGISTER ‘DSR’ ...................................................................................................................... 54
DEVICE CONTROL REGISTER ‘DCR’................................................................................................................... 55
EPP ADDRESS REGISTER ‘EPPA’ ....................................................................................................................... 55
EPP DATA REGISTERS ‘EPPD1-4’ ....................................................................................................................... 55
EXTENDED CONTROL REGISTER ‘ECR’ ............................................................................................................. 55
Page 3
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
BIDIRECTIONAL PARALLEL PORT .......................................................................................................53
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
10
10.1 SPECIFICATION ....................................................................................................................................................... 56
10.2 EEPROM DATA ORGANISATION............................................................................................................................. 56
10.2.1
ZONE0: HEADER.................................................................................................................................................. 56
10.2.2
ZONE1: LOCAL CONFIGURATION REGISTERS................................................................................................... 57
10.2.3
ZONE2: IDENTIFICATION REGISTERS ................................................................................................................ 58
10.2.4
ZONE3: PCI CONFIGURATION REGISTERS ........................................................................................................ 58
SERIAL EEPROM..................................................................................................................................56
11
12
13
12.1
12.2
13.1
13.2
13.3
OPERATING CONDITIONS ..................................................................................................................59
DC ELECTRICAL CHARACTERISTICS ..............................................................................................59
AC ELECTRICAL CHARACTERISTICS ..............................................................................................61
NON-PCI I/O BUFFERS............................................................................................................................................. 59
PCI I/O BUFFERS ..................................................................................................................................................... 60
PCI BUS.................................................................................................................................................................... 61
LOCAL BUS.............................................................................................................................................................. 61
SERIAL PORTS ........................................................................................................................................................ 62
14
15
16
TIMING WAVEFORMS ..........................................................................................................................63
PACKAGE INFORMATION...................................................................................................................70
ORDERING INFORMATION .................................................................................................................70
NOTES ...............................................................................................................................................................71
CONTACT DETAILS.........................................................................................................................................72
DISCLAIMER.....................................................................................................................................................72
Data Sheet Revision 1.3
Page 4
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
1
P
ERFORMANCE
C
OMPARISON
Feature
Internal serial channels
Integral 1284 EPP parallel port
Multi-function PCI device
Support for PCI Power Management
Zero wait-state read/write operation
No. of available Local Bus interrupt pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
Subsystem Vendor ID & Subsystem ID with
no external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16PCI954
4
yes
yes
yes
yes
1
12
yes
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C554 +
PLX9050
0
no
no
no
no
2
no
no
yes
no
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C654 +
PLX9050
0
no
no
no
no
2
no
no
yes
no
no
1.5 Mbps
n/a
64
yes
yes
yes
no
4
4
4
no
no
no
2
no
no
no
no
no
yes
Table 1: OX16PCI950 performance compared with PLX + generic UART combinations
Note 1:
Zero wait-state applies only to internal UARTs
Improvements of the OX16PCI954 over discrete solutions:
Higher degree of integration:
OX16PCI954 offers four internal 16C950 high-performance
UARTs and one bi-directional parallel port.
Improved access timing:
Access to internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
Data Sheet Revision 1.3
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
OX16PCI954 offers shadowed FIFO levels and Interrupt
status registers of internal UARTs, and Interrupt Status of
internal UARTs and MIO pins to reduce the device driver
interrupt latency.
Page 5
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