电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

V54C3256804VDLC7IPC

产品描述Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA54
产品类别存储    存储   
文件大小720KB,共56页
制造商ProMOS Technologies Inc
下载文档 详细参数 全文预览

V54C3256804VDLC7IPC概述

Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA54

V54C3256804VDLC7IPC规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
Objectid1122316467
包装说明FBGA, BGA54,9X9,32
Reach Compliance Codecompliant
ECCN代码EAR99
最长访问时间5.4 ns
最大时钟频率 (fCLK)143 MHz
I/O 类型COMMON
交错的突发长度1,2,4,8
JESD-30 代码S-PBGA-B54
JESD-609代码e0
内存密度268435456 bit
内存集成电路类型SYNCHRONOUS DRAM
内存宽度8
端子数量54
字数33554432 words
字数代码32000000
最高工作温度85 °C
最低工作温度-40 °C
组织32MX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码FBGA
封装等效代码BGA54,9X9,32
封装形状SQUARE
封装形式GRID ARRAY, FINE PITCH
电源3.3 V
认证状态Not Qualified
刷新周期8192
连续突发长度1,2,4,8,FP
最大待机电流0.001 A
最大压摆率0.2 mA
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层TIN LEAD
端子形式BALL
端子节距0.8 mm
端子位置BOTTOM

文档预览

下载PDF文档
V54C3256(16/80/40)4VD*I
256Mbit SDRAM, INDUSTRIAL TEMPERATURE
3.3 VOLT, TSOP II / FBGA PACKAGE
16M X 16, 32M X 8, 64M X 4
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
Features
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball FBGA, 54
Ball FBGA
LVTTL Interface
Single (3.0V~3.3 V)±0.3 V Power Supply
Industrial Temperature (TA): -40C to +85C
Description
The V54C3256(16/80/40)4VD*I is a four bank
Synchronous DRAM organized as 4 banks x 4Mbit
x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4.
The V54C3256(16/80/40)4VD*I achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
-40°C to +85°C
Package Outline
T/S
Access Time (ns)
6
Power
7
7PC
Std.
L
U
Temperature
Mark
I
V54C3256(16/80/40)4VD*I Rev. 1.3 December 2007
1

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2285  2420  1103  2782  1034  47  49  23  57  21 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved