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AM29F040-150LEB

产品描述Flash, 512KX8, 150ns, CQCC32, CERAMIC, LCC-32
产品类别存储    存储   
文件大小241KB,共33页
制造商AMD(超微)
官网地址http://www.amd.com
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AM29F040-150LEB概述

Flash, 512KX8, 150ns, CQCC32, CERAMIC, LCC-32

AM29F040-150LEB规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
零件包装代码QFJ
包装说明CERAMIC, LCC-32
针数32
Reach Compliance Codeunknown
ECCN代码3A001.A.2.C
最长访问时间150 ns
其他特性BULK ERASE; EMBEDDED ALGORITHM
命令用户界面YES
数据轮询YES
耐久性100000 Write/Erase Cycles
JESD-30 代码R-CQCC-N32
JESD-609代码e0
长度13.97 mm
内存密度4194304 bit
内存集成电路类型FLASH
内存宽度8
功能数量1
部门数/规模8
端子数量32
字数524288 words
字数代码512000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织512KX8
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码QCCN
封装等效代码LCC32,.45X.55
封装形状RECTANGULAR
封装形式CHIP CARRIER
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
编程电压5 V
认证状态Not Qualified
座面最大高度2.54 mm
部门规模64K
最大待机电流0.0001 A
最大压摆率0.06 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式NO LEAD
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
切换位YES
类型NOR TYPE
宽度11.43 mm
Base Number Matches1

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FINAL
Am29F040
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
s
Compatible with JEDEC-standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
s
Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
s
Minimum 100,000 write/erase cycles guaranteed
s
High performance
— 55 ns maximum access time
s
Sector erase architecture
— Uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
Also supports full chip erase.
s
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations
s
Embedded Erase Algorithms
— Automatically preprograms and erases the chip
or any combination of sectors
s
Embedded Program Algorithms
— Automatically programs and verifies data at
specified address
s
Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s
Erase suspend/resume
— Supports reading data from a sector not being
erased
s
Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
s
Enhanced power management for standby
mode
— <1
µA
typical standby current
— Standard access time from standby mode
GENERAL DESCRIPTION
The Am29F040 is a 4 Mbit, 5.0 Volt-only Flash memory
organized as 512 Kbytes of 8 bits each. The Am29F040
is offered in a 32-pin package. This device is designed
to be programmed in-system with the standard system
5.0 V V
CC
supply. A 12.0 V V
PP
is not required for
write or erase operations. The device can also be
reprogrammed in standard EPROM programmers.
The standard Am29F040 offers access times between
55 ns and 150 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE),
write enable (WE) and output enable (OE) controls.
The Am29F040 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
The Am29F040 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Typically, each sector can
be programmed and verified in less than one second.
Erase is accomplished by executing the erase com-
mand sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automati-
cally preprograms the array if it is not already pro-
grammed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
Publication#
17113
Rev:
E
Amendment/0
Issue Date:
November 1996

 
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