CY91520 Series
32-bit FR81S Microcontroller
The CY91520 series is a Cypress 32-bit microcontroller designed for automotive devices. This series contains the FR81S CPU
which is compatible with the FR family.
Note:This
series is a composition of the end of the above-mentioned each name of articles of presence, According to Presence of
sub-clock, CSV initial value and LVD initial value. Please see "Ordering Information" for details.
Features
FR81S CPU Core
32-bit RISC, load/store architecture, pipeline 5-stage
structure
Maximum operating frequency: 80 MHz (Source oscillation
= 4.0 MHz and 20 multiplied (PLL clock multiplication
system))
General-purpose register : 32 bits × 16 sets
16-bit fixed length instructions (basic instruction),
1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instruction
Bit processing instruction
Barrel shift order etc.
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Overhead reduction during branch process
Register interlock function
Easy assembler writing
The support at the built-in / instruction level of the multiplier
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of
program and data access.
Instruction compatibility with the FR Family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for
instructions and the data.
Control access privilege in both privilege mode and
user mode.
Built-in FPU (floating point arithmetic)
IEEE754 compliant
Floating-point register 32-bit × 16 sets
Peripheral Functions
Clock generation (equipped with SSCG function)
Main oscillation (4 MHz to 16 MHz)
Sub oscillation (32 kHz) or none sub oscillation
PLL multiplication rate : 1 to 20 times
Equipped with a 100 kHz CR oscillator
Built-in program flash memory capacity
CY91F522: 256 +64 KB
CY91F523: 384 + 64 KB
CY91F524: 512 + 64 KB
CY91F525: 768 + 64 KB
CY91F526: 1024 + 64 KB
Flash memory for built-in data (WorkFlash) 64 KB
Built-in RAM capacity
Main RAM
CY91F522: 48 KB
CY91F523: 48 KB
CY91F524: 64 KB
CY91F525: 96 KB
CY91F526: 128 KB
Backup RAM 8 KB
General-purpose ports:
CY91F52xB 44 sets (No sub oscillation), 42 sets (sub
oscillation)
CY91F52xD 56 sets (No sub oscillation), 54 sets (sub
oscillation)
CY91F52xF 76 sets (No sub oscillation), 74 sets (sub
oscillation)
CY91F52xJ 96 sets (No sub oscillation), 94 sets (sub
oscillation)
CY91F52xK 120 sets (No sub oscillation), 118 sets (sub
oscillation)
CY91F52xL 152 sets (No sub oscillation), 150 sets (sub
oscillation)
Included I
2
C open drain corresponding ports:16 sets
External bus interface
22-bit address, 16-bit data
DMA Controller
Up to 16 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and
software)
A/D converter (successive approximation type)
12-bit resolution : Max. 48 ch (32 ch + 16 ch)
Conversion time : 1.4 μs
Cypress Semiconductor Corporation
Document Number: 002-04662 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 25, 2018
CY91520 Series
D/A converter (R-2R type)
8-bit resolution : 2 ch
External interrupt input: 8 channels × 2 units total
16 channels
Level ("H" / "L"), or edge detection (rising or falling)
enabled
Multi-function serial communication (built-in
transmission/reception FIFO memory) : Max.12 channels
5 V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11
CMOS hysteresis input
< UART (Asynchronous serial interface) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer clock
Parity, frame, and overrun error detection functions
provided
DMA transfer support
<CSIO (Synchronous serial interface) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
SPI supported; master and slave systems supported;
5 to 16, 20, 24, 32-bit data length can be set.
Built-in dedicated baud rate generator (Master
operation)
An external clock can be entered. (Slave operation)
Overrun error detection function is provided
DMA transfer support
Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
LIN protocol revision 2.1 supported
Master and slave systems supported
Framing error and overrun error detection
LIN synch break generation and detection; LIN synch
delimiter generation
Built-in dedicated baud rate generator
An external clock can be adjusted by the reload
counter
DMA transfer support
64-transmission/reception message buffering :
2 channels (ch.1 and ch.2)
PPG: 16-bit × Max. 48 channels
LED drive output 4 channels 11 ch to 14 ch
Reload timer : 16-bit × Max.8 channels
Free-run timer :
16-bit × 3 channels
32-bit × Max 3 channels
Input capture :
16-bit × 4 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
Output compare :
16-bit × 6 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
Waveform generator : 6 channels
Up/Down counter
8-/16-bit Up/Down counter × 2 channels
Real-time clock (RTC) (for day, hours, minutes, seconds)
Main or sub oscillation frequency can be selected for
the operation clock
Calibration: Real-time clock (RTC) of the subclock drive
The main clock to sub clock ratio can be corrected by
setting the real-time clock prescaler
Clock Supervisor
Monitoring abnormality (by damaged quartz, etc.) of
suboscillation (32 kHz) (dual clock products)
of the outside and main oscillation (4 MHz)
When abnormality is detected, it switches to the CR
clock.
Initial value ON/OFF can be selected by the part
number.
Base timer : Max.2 channels
16-bit timer
Any of four PWM/PPG/PWC/reload timer functions can
be selected and used
As for the PWC function and the reload timer function,
a pair of 16-bit timers can be used as one 32-bit timer
in the cascade mode
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog (possible to set the valid range for
counter clearing)
NMI (non-maskable interrupt)
Interrupt controller
Interrupt request batch read
The interrupt existence from two or more peripherals
can be read by a series of register.
I/O relocation
Peripheral function pins can be reassigned.
Low-power consumption mode
Sleep / Stop / Watch / Sub RUN mode
Stop (power shutdown) / Watch (power shutdown)
mode
Hard assist function
< I
2
C >
2 channels ch.3 , ch.4 Standard mode/fast mode
supported.
6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode
supported.
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
Standard mode (Max. 100 kbps) / fast mode (Max. 400
kbps) supported
DMA transfer supported (for transmission only)
CAN Controller (CAN) : 3 channels
Transfer speed : Up to 1 Mbps
128-transmission/reception message buffering :
1 channel (ch.0),
Document Number: 002-04662 Rev. *H
Page 2 of 281
CY91520 Series
Power-on reset
Low-voltage detection reset (independently monitor the
external power supply and the internal power supply)
The external power supply can select initial value
ON/OFF by the part number.
Device Package : 176/144/120/100/80/64
CMOS 90 nm Technology
Power supplies
5 V Power supply
The internal 1.2 V is generated from 5 V with the
voltage step-down circuit
Document Number: 002-04662 Rev. *H
Page 3 of 281
CY91520 Series
Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
Product Lineup .......................................................................................................................................... 5
Pin Assignment ....................................................................................................................................... 12
Pin Description ........................................................................................................................................ 18
I/O Circuit Type ....................................................................................................................................... 35
Handling Precautions .............................................................................................................................. 40
Handling Devices .................................................................................................................................... 44
Block Diagram ......................................................................................................................................... 47
Memory Map ........................................................................................................................................... 53
I/O Map.................................................................................................................................................... 55
10. Interrupt Vector Table ............................................................................................................................ 109
11. Electrical Characteristics ....................................................................................................................... 133
12. Example Characteristics ....................................................................................................................... 193
13. Ordering Information CY91F52xxxB
*1
................................................................................................... 196
14. Ordering Information CY91F52xxxC
*1
................................................................................................... 203
15. Ordering Information CY91F52xxxD ..................................................................................................... 210
16. Ordering Information CY91F52xxxE ..................................................................................................... 214
17. Package Dimensions ............................................................................................................................ 218
18. Errata..................................................................................................................................................... 225
19. Major Changes ...................................................................................................................................... 228
Document Number: 002-04662 Rev. *H
Page 4 of 281
CY91520 Series
1.
Product Lineup
CY91F523B
CY91F524B
CY91F525B
On chip PLL Clock multiple method
12.5 ns (80 MHz)
(256+64) KB
(384+64) KB
(512+64) KB
(768+64) KB
64 KB
(48+8) KB
(64+8) KB
(96+8) KB
CY91F522B
CY91F526B
Product Lineup Comparison 64 Pins
System Clock
Minimum instruction execution time
Flash Capacity (Program)
(1024+64) KB
Flash Capacity (Data)
RAM Capacity
(128+8) KB
External BUS I/F
None
(22 address/16 data/4 cs)
DMA Transfer
16 ch
16-bit Base Timer
None
Free-run Timer
16 bit × 3 ch, 32 bit × 1 ch
Input capture
16 bit × 4 ch, 32 bit × 5 ch
Output Compare
16 bit × 6 ch, 32 bit × 4 ch
16-bit Reload Timer
7 ch
PPG
16 bit × 21 ch
Up/down Counter
2 ch
Clock Supervisor
Yes
External Interrupt
8 ch × 2 units
A/D converter
12 bit × 13 ch (1 unit), 12 bit × 13 ch (1 unit)
D/A converter (8 bit)
1 ch
Multi-Function Serial Interface
8 ch
*1
CAN
64 msg × 2 ch/128 msg × 1 ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
44 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6 ch
NMI request function
Yes
Operation guaranteed temperature (T
A
)
-40 °C to +125 °C
Power supply
2.7 V to 5.5 V
*2
Package
LQD064
2
C (standard mode).
*1: Only channel 5, channel 6 and channel 11 support the I
*2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to 3.024 V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *H
Page 5 of 281
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
