a
FEATURES
Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/ s
Low Droop Rate
T
A
= 25 C: 0.1 mV/ms
T
A
= 125 C: 10 mV/ms
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form
Monolithic Peak Detector
with Reset-and-Hold Mode
PKD01
FUNCTIONAL BLOCK DIAGRAM
+IN
–IN
OUTPUT
V+
V–
–
CMP
+
LOGIC
GND
V–
OUTPUT
BUFFER
GATED
"g
m
"
AMP
A
–
D
1
+
C
OUTPUT
DET
–IN
+IN
–
+
–IN
+IN
–
B
+
GATED
"g
m
"
AMP
PKD01
GENERAL DESCRIPTION
The PKD01 tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
PKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
sacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
when charge injection and droop rate error reduction are
primary goals.
Innovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (g
m
) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
g
m
amplifiers simplify internal frequency compensation, minimize
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
steered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
ently low zero-scale error is further reduced by active Zener-Zap
trimming to optimize overall accuracy.
RST
RST
0
0
1
1
DET
0
1
1
0
OPERATIONAL MODE
PEAK DETECT
PEAK HOLD
RESET
INDETERMINATE
C
H
SWITCHES SHOWN FOR:
RST = “0,”
DET
= “0”
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Through the
DET
control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
PKD01–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V =
S
15 V, C
H
= 1000 pF, T
A
= 25 C, unless otherwise noted.)
PKD01A/E
Min Typ Max
2
2
80
20
25
0.4
90
96
±
11
0.5
80
41
45
4
3
150
40
10
74
76
±
10
66
70
PKD01F
Min Typ Max Unit
3
3
80
20
25
0.4
90
96
±
11
0.5
80
41
45
7
6
250
75
mV
mV
nA
nA
V/mV
MHz
dB
dB
V
V/µs
dB
µs
µs
Parameter
g
m
AMPLIFIERS A, B
Zero-Scale Error
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain
Open-Loop Bandwidth
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
1
Slew Rate
Feedthrough Error
1
Acquisition Time to
0.1% Accuracy
1
Acquisition Time to
0.01% Accuracy
1
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
1
Low Output Voltage
“OFF” Output Leakage Current
Output Short-Circuit Current
Response Time
2
DIGITAL INPUTS – RST,
DET
2
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Current
Logic “0” Input Current
MISCELLANEOUS
Droop Rate
3
Output Voltage Swing:
Amplifier C
Short-Circuit Current:
Amplifier C
Switch Aperture Time
Switch Switching Time
Slew Rate: Amplifier C
Power Supply Current
Symbol Conditions
V
ZS
V
OS
I
B
I
OS
A
V
BW
CMRR
PSRR
V
CM
SR
R
L
= 10 kΩ, V
O
=
±
10 V
A
V
= 1
–10 V
≤
V
CM
≤
+10 V
±
9 V
≤
V
S
≤ ±
18 V
∆V
IN
= 20 V, DET = 1, RST = 0
18
80
86
±
10
66
t
AQ
t
AQ
20 V Step, A
VCL
= +1
20 V Step, A
VCL
= +1
70
V
OS
I
B
I
OS
A
V
CMRR
PSRR
V
CM
V
OL
I
L
I
SC
t
S
2 kΩ Pull-Up Resistor to 5 V
–10 V
≤
V
CM
≤
+10 V
±
9 V
≤
V
S
≤ ±
18 V
I
SINK
≤
5 mA, Logic GND = 0 V
V
OUT
= 5 V
V
OUT
= 5 V
5 mV Overdrive, 2 kΩ Pull-Up
Resistor to 5 V
0.5
700
75
5
7.5
82
106
76
90
±
11.5
±
12.5
–0.2 +0.15
25
7
12
150
1.5
1000
300
+0.4
80
45
1
700
75
3.5
7.5
82
106
76
90
±
11.5
±
12.5
–0.2 +0.15
25
7
12
150
3
mV
1000 nA
300 nA
V/mV
dB
dB
V
+0.4 V
80
µA
45
mA
ns
V
H
V
L
I
INH
I
INL
V
DR
V
OP
I
SC
t
AP
ts
SR
I
SY
2
V
H
= 3.5 V
V
L
= 0.4 V
T
J
= 25°C
T
A
= 25°C
DET
= 1
R
L
= 2.5 kΩ
0.02
1.6
0.01
0.02
±
11.5
±
12.5
7
15
75
50
2.5
5
40
0.8
1
10
0.07
0.15
2
0.02
1.6
0.01
0.03
±
11
7
±
12
15
75
50
2.5
6
40
0.8
1
10
0.1
0.20
V
V
µA
µA
mV/ms
mV/ms
V
mA
ns
ns
V/µs
mA
R
L
= 2.5 kΩ
No Load
7
9
NOTES
1
Guaranteed by design.
2
DET
= 1, RST = 0.
3
Due to limited production test times, the droop current corresponds to junction temperature (T
J
). The droop current vs. time (after power-on) curve clarified this point. Since
most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T
A
) also. The warmed-up (T
A
) droop current specification is correlated
to the junction temperature (T
J
) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (T
A
) temperature specifications
are not subject to production testing.
Specifications subject to change without notice.
–2–
REV. A
ELECTRICAL CHARACTERISTICS
Parameter
“g
m
” AMPLIFIERS A, B
Zero-Scale Error
Input Offset Voltage
Average Input Offset Drift
1
Input Bias Current
Input Offset Current
Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
1
Slew Rate
Acquisition Time to 0.1% Accuracy
1
COMPARATOR
Input Offset Voltage
Average Input Offset Drift
1
Input Bias Current
Input Offset Current
Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
1
Low Output Voltage
OFF Output Leakage Current
Output Short-Circuit Current
Response Time
DIGITAL INPUTS – RST,
DET
2
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Current
Logic “0” Input Current
MISCELLANEOUS
Droop Rate
3
(@ V
S
= 15 V, C
H
= 1000 pF, –55 C
≤
T
A
≤
+125 C for PKD01AY, –25 C
≤
T
A
≤
+85 C for
PKD01EY, PKD01FY and 0 C
≤
T
A
≤
+70 C for PKD01EP, PKD01FP, unless otherwise noted.)
PKD01A/E
PKD01F
Min Typ Max Min Typ Max
4
3
–9
160
30
7.5 9
74 82
80 90
±
10
±
11
0.4
60
2
–4
1000
100
6.5
100
82
7
6
–24
250
100
5
72
70
±
10
6
5
–9
160
30
9
80
90
±
11
0.4
60
2
–4
1100
100
6.5
92
86
12
10
–24
500
150
Unit
mV
mV
µV/°C
nA
nA
V/mV
dB
dB
V
V/µs
µs
mV
µV/°C
nA
nA
V/mV
dB
dB
V
V
µA
mA
ns
V
V
µA
µA
mV/ms
mV/ms
V
40
mA
ns
V/µs
mA
PKD01
Symbol Conditions
V
ZS
V
OS
TCV
OS
I
B
I
OS
A
V
CMRR
PSRR
V
CM
SR
t
AQ
V
OS
TCV
OS
I
B
I
OS
A
V
CMRR
PSRR
V
CM
V
OL
I
L
I
SC
t
S
R
L
= 10 kΩ, V
O
=
±
10 V
–10 V
≤
V
CM
≤
+10 V
±
9 V
≤
V
S
≤ ±
18 V
20 V Step, A
VCL
= +1
2.5
–6
2000
600
5
–6
2000
600
2 kΩ Pull-Up Resistor to 5 V
–10 V
≤
V
CM
≤
+10 V
±
9 V
≤
V
S
≤ ±
18 V
4
2.5
80
80
72
72
±
11
±
11
I
SINK
≤
5 mA, Logic GND = 0 V –0.2 +0.15 +0.4 –0.2
V
OUT
= 5 V
25
100
V
OUT
= 5 V
6
10
45
6
5 mV Overdrive, 2 kΩ Pull-Up
Resistor to 5 V
200
2
V
H
= 3.5 V
V
L
= 0.4 V
0.02
2.5
1.2
2.4
±
11
±
12
6
R
L
= 2.5 kΩ
No Load
12
75
2
5.5
40
0.8
1
15
10
20
2
+0.15 +0.4
100 180
10
45
200
V
H
V
L
I
INH
I
INL
V
DR
0.02
2.5
3
6
±
10.5
±
12
6
12
75
2
6.5
0.8
1
15
15
20
T
J
= Max Operating Temp.
T
A
= Max Operating Temp.
DET
= 1
R
L
= 2.5 kΩ
Output Voltage Swing
Amplifier C
Short-Circuit Current
Amplifier C
Switch Aperture Time
Slew Rate: Amplifier C
Power Supply Current
V
OP
I
SC
t
AP
SR
I
SY
8
10
NOTES
1
Guaranteed by design.
2
DET
= 1, RST = 0.
3
Due to limited production test times, the droop current corresponds to junction temperature (T
J
). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T
A
) also. The warmed-up (T
A
) droop current
specification is correlated to the junction temperature (T
J
) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
Ambient (T
A
) temperature specifications are not subject to production testing.
Specifications subject to change without notice.
REV. A
–3–
PKD01
ABSOLUTE MAXIMUM RATINGS
1, 2
ORDERING GUIDE
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Input Voltage . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Logic and Logic Ground
Voltage . . . . . . . . . . . . . . . . . . . . . . Equal to Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Amplifier A or B Differential Input Voltage . . . . . . . . . .
±
24 V
Comparator Differential Input Voltage . . . . . . . . . . . . .
±
24 V
Comparator Output Voltage
. . . . . . . . . . . . . . . . . . . . . . Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration . . . . . . . . . . Indefinite
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Storage Temperature Range
PKD01AY, PKD01EY, PKD01FY . . . . . –65°C to +150°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
PKD01AY . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
PKD01EY, PKD01FY . . . . . . . . . . . . . . . . –25°C to +85°C
PKD01EP, PKD01FP . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Model
2
Temperature
Range
–55°C to +85°C
–25°C to +85°C
–25°C to +85°C
0°C to 70°C
0°C to 70°C
Package
Description
Cerdip
Cerdip
Cerdip
Plastic DIP
Plastic DIP
Package
Option
Q-14
Q-14
Q-14
N-14
N-14
PKD01AY
PKD01EY
PKD01FY
PKD01EP
PKD01FP
NOTES
1
Burn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.
PIN CONFIGURATION
RST
V+
OUTPUT
C
H
–IN A
+IN A
V–
DET
LOGIC GND
COMP OUT
PKD01
–IN C
+IN C
–IN B
+IN B
THERMAL CHARACTERISTICS
Package Type
14-Lead Hermetic DIP (Y)
14-Lead Plastic DIP (P)
JA
*
JC
Unit
°C/W
°C/W
99
76
12
33
*θ
JA
is specified for worst-case mounting conditions, i.e.,
θ
JA
is specified for device
in socket for cerdip and PDIP packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the PKD01 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
DICE CHARACTERISTICS
–4–
REV. A
PKD01
WAFER TEST LIMITS
(@ V =
S
15 V, C
H
= 1000 pF, T
A
= 25 C, unless otherwise noted.)
Symbol
V
ZS
V
OS
I
B
I
OS
A
V
CMRR
PSRR
V
CM
Conditions
PKD01N
Limit
7
6
250
75
10
74
76
±
11.5
66
3
1000
300
3.5
82
76
±
11.5
0.4
–0.2
80
45
7
2
0.8
1
10
0.1
0.20
±
11
40
7
9
0.5
41
45
150
75
50
2.5
Unit
mV max
mV max
nA max
nA max
V/mV min
dB min
dB min
V min
dB min
mV max
nA max
nA max
V/mV min
dB min
dB min
V min
V max
V min
µA
max
mA min
mA min
V min
V max
µA
max
µA
max
mV/ms max
mV/ms max
V min
mA max
mA min
mA max
V/µs
µs
µs
ns
ns
ns
V/µs
Parameter
“g
m
” AMPLIFIERS A, B
Zero-Scale Error
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
1
Feedthrough Error
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain
1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
1
Low Output Voltage
“OFF” Output Leakage Current
Output Short-Circuit Current
DIGITAL INPUTS–RST,
DET
2
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Current
Logic “0” Input Current
MISCELLANEOUS
Droop Rate
3
Output Voltage Swing Amplifier C
Short-Circuit Current Amplifier C
Power Supply Current
g
m
AMPLIFIERS A, B
Slew Rate
Acquisition Time
1
COMPARATOR
Response Time
MISCELLANEOUS
Switch Aperture Time
Switching Time
Buffer Slew Rate
R
L
= 10 kΩ, V
O
=
±
10 V
–10 V
≤
V
CM
≤
+10 V
±
9 V
≤
V
S
≤ ±
18 V
∆V
IN
= 20 V,
DET
= 1, RST = 0
V
OS
I
B
I
OS
A
V
CMRR
PSRR
V
CM
V
OL
I
L
I
SC
2 kΩ Pull-Up Resistor to 5 V
–10 V
≤
V
CM
≤
+10 V
±
9 V
≤
V
S
≤ ±
18 V
I
SINK
≤
5 mA, Logic GND = 5 V
V
OUT
= 5 V
V
OUT
= 5 V
V
H
V
L
I
INH
I
INL
V
DR
V
OP
I
SC
I
SY
SR
t
A
t
A
V
H
= 3.5 V
V
L
= 0.4 V
T
J
= 25°C,
T
A
= 25°C
R
L
= 2.5 kΩ
No Load
0.1% Accuracy, 20 V Step, A
VCL
= 1
0.01% Accuracy, 20 V Step, A
VCL
= 1
5 mV Overdrive, 2 kΩ Pull-Up Resistor to 5 V
t
AP
t
S
SR
R
L
= 2.5 kΩ
NOTES
1
Guaranteed by design.
2
DET
= 1, RST = 0.
3
Due to limited production test times, the droop current corresponds to junction temperature (T
J
). The droop current vs. time (after power-on) curve clarifies this
point. Since most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (T
A
) also. The warmed-up (T
A
) droop current
specification is correlated to the junction temperature (T
J
) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature.
Ambient (T
A
) temperature specifications are not subject to production testing.
REV. A
–5–
PCB设计
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