56F803
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F803
Rev. 15
01/2007
freescale.com
56F803 General Description
•
•
•
•
Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
31.5K
×
16-bit words (64KB) Program Flash
512
×
16-bit words (1KB) Program RAM
4K
×
16-bit words (8KB) Data Flash
2K
×
16-bit words (4KB) Data RAM
2K
×
16-bit words (4KB) Boot Flash
Up to 64K
×
16-bit words each of external Program
and Data memory
•
•
•
•
•
•
•
•
•
•
6-channel PWM module
Two 4-channel 12-bit ADCs
Quadrature Decoder
CAN 2.0 B module
Serial Communication Interface (SCI)
Serial Peripheral Interface (SPI)
Up to two General Purpose Quad Timers
JTAG/OnCE
TM
port for debugging
16 shared GPIO lines
100–pin LQFP package
•
•
•
•
•
•
6
3
3
PWM Outputs
Current Sense Inputs
Fault Inputs
PWMA
RESET
IRQA
EXTBOOT
IRQB
6
JTAG/
OnCE
Port
VCAPC V
DD
2
6
V
SS
6*
Digital Reg
Analog Reg
V
DDA
V
SSA
4
4
A/D1
A/D2
VREF
ADC
Interrupt
Controller
Low Voltage
Supervisor
4
Quadrature
Decoder 0 /
Quad Timer A
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Quad Timer B
Quad Timer C
Quad Timer D
2
CAN 2.0A/B
2
2
SCI
or
GPIO
COP/
Watchdog
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
Boot Flash
2048 x 16 Flash
•
PAB
•
•
PDB
•
•
•
•
IPBB
CONTROLS
16
PLL
CLKO
XDB2
CGDB
XAB1
XAB2
16-Bit
56800
Core
XTAL
Clock Gen
EXTAL
•
INTERRUPT
CONTROLS
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
4
SPI
or
GPIO
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
A[00:05]
6
10
16
PS Select
DS Select
WR Enable
RD Enable
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
56F803 Block Diagram
*
includes TCS pin which is reserved for factory use and is tied to VSS
56F803 Technical Data, Rev. 15
Freescale Semiconductor
3
Part 1 Overview
1.1 56F803 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
×
16
-
bit parallel Multiplier-Accumulator (MAC)
Two 36
-
bit accumulators, including extension bits
16
-
bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
•
•
Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 31.5K
×
16-bit words of Program Flash
— 512K
×
16
-
bit words of Program RAM
— 4K
×
16
-
bit words of Data Flash
— 2K
×
16
-
bit words of Data RAM
— 2K
×
16
-
bit words of Boot Flash
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
×
16 bits of Data memory
— As much as 64K
×
16 bits of Program memory
1.1.3
•
Peripheral Circuits for 56F803
Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault
inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes,
supports Freescale’s patented dead time distortion correction
Two 12
-
bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and
PWM modules can be synchronized
Quadrature Decoder with four inputs (shares pins with Quad Timer)
•
•
56F803 Technical Data, Rev. 15
4
Freescale Semiconductor
56F803 Description
•
•
•
•
•
•
•
•
•
•
Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external
pins and Timer D with two pins
CAN 2.0 B module with 2-pin ports for transmit and receive
Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
Computer Operating Properly (COP) Watchdog timer
Two dedicated external interrupt pins
Sixteen multiplexed General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
•
•
•
•
Energy Information
Fabricated in high-density CMOS with 5V
-
tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F803 Description
The 56F803 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact device and control code.
The instruction set is also highly efficient for C compilers to enable rapid development of optimized
control applications.
The 56F803 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external
dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory.
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
56F803 Technical Data, Rev. 15
Freescale Semiconductor
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
