Features
PC603e Microprocessor (Embedded PowerPC
®
Core) at 166-450 MHz
603e Core with 16K Inst and 16K Data Caches
64-bit 60x Bus, 32-bit Local/PCI Bus
128K ROM, 32K IRAM, 32K DPRAM
Three FCCs Supporting ATM, 10/100 Ethernet or HDLC
256 HDLC Channels, 8 TDMs
4 SCCs, 2 SMCs, SPI, I2C
Memory Controller Built from SDRAM, UPM, GPCM Machines
New Features - USB, RMII, UTOPIA Improvements
Performance
– 400 MHz CPU, 250 MHz CPM, 83 MHz Bus
– Less than 2W at Full Performance, 1.5V
•
Technology
– HiP7AP, 3.3V I/O, 1.5V Core
– 480 TBGA, 37.5 × 37.5 mm, 1.27 mm Ball Pitch
•
•
•
•
•
•
•
•
•
•
Integrated
Communication
Processors
PC8280
PowerQUICC II
Preliminary
Description
This document contains detailed information about power considerations, DC/AC
electrical characteristics, and AC timing specifications for 0.13 µm (HiP7) members of
the PowerQUICC II
™
family of integrated communications processors: the PC8280
and the PC8270 (collectively called 'the PC8280' throughout this document).
Screening/Quality/Packaging
This product is manufactured in full compliance with:
•
Upscreening based upon Atmel standards
•
Military temperature range (T
amb
= -55°C, T
J
= +125°C)
•
480-ball Tape Ball Grid Array package (TBGA 37.5 × 37.5 mm)
TP suffix
TBGA480
Tape Ball Grid Array
5450C–HIREL–07/06
1. Overview
Table 1-1
shows the functionality supported by the PC8280.
Table 1-1.
PC8280 PowerQUICC II Functionality
PC8270
Functionality
Package
480 TBGA
4
–
3
16
16
3
0
1
Yes
–
–
1
–
PC8280
480 TBGA
4
–
3
16
16
3
2
2
Yes
Yes
Yes
1
–
Serial communications controllers (SCCs)
QUICC multi-channel controller (QMC)
Fast communication controllers (FCCs)
I-Cache (Kbyte)
D-Cache (Kbyte)
Ethernet (10/100)
UTOPIA II Ports
Multi-channel controllers (MCCs)
PCI bridge
Transmission convergence (TC) layer
Inverse multiplexing for ATM (IMA)
Universal serial bus (USB) 2 full/low rate
Security engine (SEC)
2
PC8280 [Preliminary]
5450C–HIREL–07/06
PC8280 [Preliminary]
Figure 1-1.
PC8280 Block Diagram
16 Kbytes
I-Cache
I-MMU
G2_LE Core
16 Kbytes
D-Cache
D-MMU
System Interface Unit
(SIU)
Bus Interface Unit
60x-to-PCI
Bridge
60x-to-Local
Bridge
Memory Controller
Serial
DMAs
4 Virtual
IDMAs
Clock Counter
System Functions
60x Bus
PCI Bus
32 bits, up to 66 MHz
or
Local Bus
32 bits, up to 100 MHz
Communication Processor Module (CPM)
Timers
Parallel I/Q
Baud Rate
Generators
Interrupt
Controller
32 KB
Instruction
RAM
32 KB
Data
RAM
32-bit RISC Microcontroller
and Program ROM
IMA1
Microcode
MCC1
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4/
USB
SMC1
SMC2
SPI
I
2
C
TC Layer Hardware1
Time Slot Assigner
Serial Interface2
8 TDM Ports2
3 MII or RMII
Port
2 UTOPIA
Ports3
Non-Multiplexed
I/O
Notes:
1. PC8280 only (not on PC8270)
2. PC8280 has 2 serial interface (SI) blocks and 8 TDM ports. PC8270 has only 1 SI block and 4 TDM ports (TDM2[A–D]).
3. PC8280 only (not on PC8270)
1.1
Features
The major features of the PC8280 are as follows:
• Dual-issue integer (G2_LE) core
A core version of the EC603e microprocessor
System core microprocessor supporting frequencies of 166–450 MHz
Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
Architecture-compliant memory management unit (MMU)
Common on-chip processor (COP) test interface
High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)
Supports bus snooping for data cache coherency
3
5450C–HIREL–07/06
Floating-point unit (FPU)
• Separate power supply for internal logic and for I/O
• Separate PLLs for G2_LE core and for the CPM
G2_LE core and CPM can run at different frequencies for power/performance optimization
Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1,
8:1 ratios
Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
• 64-bit data and 32-bit address 60x bus
Bus supports multiple master designs
Supports single- and four-beat burst transfers
64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
Single-master bus, supports external slaves
Eight-beat burst transfers
32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
• 60x-to-PCI bridge
Programmable host bridge and agent
32-bit data bus, 66.67/83.3/100 MHz, 3.3V
Synchronous and asynchronous 60x and PCI clock modes
All internal address space available to external PCI host
DMA for memory block transfers
PCI-to-60x address remapping
• PCI bridge
PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
On-chip arbitration
Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
PCI host bridge or periphera
l
capabilities
Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI–
Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the PC8280) required by the PCI standard as well as message and
doorbell registers
Supports the
I
2
O
standard
4
PC8280 [Preliminary]
5450C–HIREL–07/06
PC8280 [Preliminary]
Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0
August 3, 1998)
Support for 66.67/83.33/100 MHz, 3.3V specification
60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port
Uses the local bus signals, removing need for additional pins
• System Interface Unit (SIU)
Clock synthesizer
Reset controller
Real-time clock (RTC) register
Periodic interrupt timer
Hardware bus monitor and software watchdog timer
IEEE
®
1149.1 JTAG test access port
• 12-bank memory controller
Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
Byte write enables and selectable parity generation
32-bit address decodes with programmable bank size
Three user-programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
Byte selects for 64-bus width (60x) and byte selects for 32-bus width (local)
Dedicated interface logic for SDRAM
• CPU core can be disabled and the device can be used in slave mode to an external core
• Communications Processor Module (CPM)
Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible sup-
port for communications protocols
Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-
Kbyte dual-port instruction RAM and DMA controller
Serial DMA channels for receive and transmit on all serial channels
Parallel I/O registers with open-drain and interrupt capability
Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII) or reduced media independent interface (RMII)
– ATM: Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K
external connections (no ATM support for the PC8270)
– Transparent
– HDLC: Up to T3 rates (clear channel)
5
5450C–HIREL–07/06
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