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V54C3256804VAC7PC

产品描述Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA60
产品类别存储    存储   
文件大小785KB,共49页
制造商Mosel Vitelic Corporation ( MVC )
官网地址http://www.moselvitelic.com
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V54C3256804VAC7PC概述

Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA60

V54C3256804VAC7PC规格参数

参数名称属性值
是否Rohs认证不符合
Objectid103130456
包装说明FBGA, BGA60,8X15,32
Reach Compliance Codeunknown
ECCN代码EAR99
最长访问时间5.4 ns
最大时钟频率 (fCLK)143 MHz
I/O 类型COMMON
交错的突发长度1,2,4,8
JESD-30 代码R-PBGA-B60
JESD-609代码e0
内存密度268435456 bit
内存集成电路类型SYNCHRONOUS DRAM
内存宽度8
端子数量60
字数33554432 words
字数代码32000000
最高工作温度70 °C
最低工作温度
组织32MX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码FBGA
封装等效代码BGA60,8X15,32
封装形状RECTANGULAR
封装形式GRID ARRAY, FINE PITCH
电源3.3 V
认证状态Not Qualified
刷新周期8192
连续突发长度1,2,4,8
最大待机电流0.001 A
最大压摆率0.24 mA
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子节距0.8 mm
端子位置BOTTOM

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V54C3256(16/80/40)4V(T/C)
256Mbit SDRAM
3.3 VOLT, TSOP II / TRUECSP PACKAGE
16M X 16, 32M X 8, 64M X 4
PRELIMINARY
s
s
s
s
s
s
CILETIV LESOM
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
Features
s
s
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s
s
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 60 Ball TrueCSP and 54 Pin TSOP II
LVTTL Interface
Single +3.3 V
±0.3
V Power Supply
Description
The V54C3256(16/80/40)4V(T/C) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3256(16/80/40)4V(T/C) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
s
s
s
s
s
s
s
s
s
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/C
Access Time (ns)
6
Power
8PC
7PC
7
Std.
L
Temperature
Mark
Blank
V54C3256(16/80/40)4V(T/C) Rev. 1.0 September 2001
1

 
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